AD1803 Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге

Компоненты Описание

производитель

AD1803

Modem/Telephony Codec

Analog Devices 

THEORY OF OPERATION

SERIAL INTERFACE MODE SELECTION

When power is first applied to the AD1803, RESET must be

asserted (RESET pin driven low), and kept asserted until the

power has stabilized. While RESET is asserted, the AD1803’s

serial interface mode is chosen by the state of Pin 12

(G[3]/WAKE) and Pin 13 (G[2]).

Table 7.

Pin 12 Pin 13

High High

High Low

Low High

Low Low

Mode Chosen

AC '97 Mode—Primary Device (ID: 00)

AC '97 Mode—Secondary Device (ID: 01)

AC '97 Mode—Secondary Device (ID: 10)

DSP Mode

Note that Pin 12 and Pin 13 have weak pull-up devices internal

to the AD1803 that are enabled by default. Therefore, if these

pins are floated, AC '97 primary mode is chosen. When RESET

is deasserted (RESET pin driven high) for the first time after

power is applied, the states of Pin 12 and Pin 13 are latched,

locking in serial interface mode. Subsequent changes of the

logic level presented on Pin 12 and Pin 13 have no effect on

serial port mode until power is removed from the AD1803.

After this first deassertion of RESET, Pin 12 and Pin 13 take

on new roles and serve as general-purpose I/O control pins.

The AD1803 does not need an active clock source for proper

operation during this mode selection.

SERIAL INTERFACE BEHAVIOR AND PROTOCOL

WHEN IN AC '97 MODE

The AD1803 serial interface is compatible with the AC '97

Rev 2.1 specification as either a primary or a secondary

modem/handset codec device. Consult this specification

for complete behavioral details.

AD1803

By default the AD1803 uses Slot 5 to send and receive sample

data, but this can be changed to Slot 10 or Slot 11. See the

SPCHN bit, SPGBP bit, SPDSS bit, SPISO bit, SPDL1 bit, and

SPDL0 bit in Register 0x5E for additional AC '97 mode con-

figuration enhancements.

AC '97 INTERFACE MODES

Primary Mode

Entered if G[3] pin and G[2] pin are high when the RESET pin

is deasserted for the first time:

• AD1803 is the timing master: drives BIT_CLK at

12.288 MHz.

• AD1803 accepts the 48 kHz SYNC timing signal.

• AD1803 requires a crystal or clock on XTALI (see the

XTAL1 bit and XTAL0 bit in Register 0x5C for frequency).

Secondary Mode

Entered if the G[3] pin is high and G[2] pin is low when the

RESET pin is deasserted for the first time or if the G[3] pin is

low and the G[2] pin is high when the RESET pin is deasserted

for the first time:

• AD1803 is the timing slave: accepts BIT_CLK at

12.288 MHz.

• AD1803 accepts the 48 kHz SYNC timing signal.

• AD1803 does not require a crystal or clock on XTALI

(see the XTAL1 bit and XTAL0 bit in Register 0x5C for

frequency), unless wake from an event during RESET is

desired. XTALI okay here?

SLOT #

0

1

2

3

4

5

6

7

8

9

10

11

12

SYNC

SDATA_OUT

TAG

CMD CMD

ADDR DATA

PCM

L

PCM

R

LINE1 PCM PCM PCM

DAC CENTER L SURR R SURR

(OUTPUT FROM CONTROLLER/DSP – INPUT TO AD1803)

PCM

LFE

LINE2

DAC

HSET

DAC

I/O

CTRL

SDATA_IN

TAG STATUS STATUS PCM

ADDR DATA

L

PCM

R

LINE1

ADC

MIC RSRVD RSRVD RSRVD

ADC

(INPUT TO CONTROLLER/DSP – OUTPUT FROM AD1803)

Figure 10. AC '97 Interface Timing

LINE2

ADC

HSET I/O

AD STATUS

Rev. A | Page 11 of 32

Share Link: