S-24C32C Просмотр технического описания (PDF) - Seiko Instruments Inc

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S-24C32C

2-WIRE SERIAL E2PROM

Seiko Instruments Inc 

Rev.4.0_02_H

2-WIRE SERIAL E2PROM

S-24C32C/64C

7. Read

7. 1 Current address read

Either in writing or in reading the S-24C32C/64C holds the last accessed memory address. The memory address

is maintained as long as the power voltage does not decrease less than the operating voltage.

The master device can read the data at the memory address of the current address pointer without assigning the

word address as a result, when it recognizes the position of the address pointer in the S-24C32C/64C. This is

called “Current Address Read”.

In the following the address counter in the S-24C32C/64C is assumed to be “n”.

When the S-24C32C/64C receives a 7-bit device address and a 1-bit read / write instruction code set to “1”

following a start condition, it responds with an acknowledge.

Next, an 8-bit data at the address “n” is sent from the S-24C32C/64C synchronous to the SCL clock. The address

counter is incremented and the content of the address counter becomes n+1.

The master device outputs stop condition not an acknowledge, the reading of S-24C32C/64C is ended.

S

T

R

A

E

R

DEVICE

A

T

ADDRESS

D

NO ACK from

Master Device

S

T

O

P

SDA LINE

1 0 1 0 A2 A1 A0 1 D7 D6 D5 D4 D3 D2 D1 D0

M

LR A

DATA

S

S/ C

B

BW K

Figure 18 Current Address Read

Attention should be paid to the following point on the recognition of the address pointer in the S-24C32C/64C.

In Read, the memory address counter in the S-24C32C/64C is automatically incremented after output of the 8th

bit of the data. In Write, on the other hand, the upper bits of the memory address (the upper bits of the word

address*1) are left unchanged and are not incremented.

*1. In the S-24C32C, the upper 7 bits of the word address.

In the S-24C64C, the upper 8 bits of the word address.

17

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