ADSP-BF539F(RevA) Просмотр технического описания (PDF) - Analog Devices

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производитель

ADSP-BF539F
(Rev.:RevA)

Blackfin Embedded Processor

Analog Devices 

ADSP-BF539/ADSP-BF539F

VDDINT (1.25V)

FB

0.01MF

ADSP-BF539F

MPIVDD

MTXON

0.1MF

MXEGND

MTX

MRX

MRXON

5V

POWER GATING CIRCUIT

27 6

5V

MOST FOT

Rx_Vdd

Tx_Vdd

TX_Data

RX_Data

Status

49.152MHz OSCILLATOR

CLKO

MXI

MXO

MLF

R1

220 6

C1

0.1MF

C2

0.01MF

MXEGND

RFS0

MFS

MMCLK

MBCLK

TSCLK0

RSCLK0

DT0PRI

336

336

33 6

L/RCLK

MCLK

BCLK

SDATA

AUDIO DAC

MOST

NETWORK

AUDIO

CHANNELS

Figure 9. Example Connections of ADSP-BF539/ADSP-BF539F to MOST Network

MXVR BOARD LAYOUT GUIDELINES

MLF pin

• Capacitors:

C1: 0.1 μF (PPS type, 2% tolerance recommended)

C2: 0.01 μF (PPS type, 2% tolerance recommended)

• Resistor:

R1: 220 Ω (1% tolerance)

• The RC network connected to the MLF pin should be

located physically close to the MLF pin on the board.

• The RC network should be wired up and connected to the

MLF pin using wide traces.

• The capacitors in the RC network should be grounded to

MXEGND.

• The RC network should be shielded using MXEGND

traces.

• Avoid routing other switching signals near the RC network

to avoid crosstalk.

MXI driven with external clock oscillator IC (recommended)

• MXI should be driven with the clock output of a

49.152 MHz or 45.1584 MHz clock oscillator IC.

• MXO should be left unconnected.

• Avoid routing other switching signals near the oscillator

and clock output trace to avoid crosstalk. When not possi-

ble, shield traces with ground.

MXI/MXO with external crystal

• The crystal must be a 49.152 MHz or 45.1584 MHz funda-

mental mode crystal.

• The crystal and load capacitors should be placed physically

close to the MXI and MXO pins on the board.

• The load capacitors should be grounded to MXEGND.

• The crystal and load capacitors should be wired up using

wide traces.

• Board trace capacitance on each lead should not be more

than 3 pF.

• Trace capacitance plus load capacitance should equal the

load capacitance specification for the crystal.

• Avoid routing other switching signals near the crystal and

components to avoid crosstalk. When not possible, shield

traces and components with ground.

MXEGND–MXVR crystal oscillator and MXVR PLL ground

• Should be routed with wide traces or as ground plane.

• Should be tied together to other board grounds at only one

point on the board.

• Avoid routing other switching signals near to MXEGND to

avoid crosstalk.

MXEVDD–MXVR crystal oscillator 3.3 V power

• Should be routed with wide traces or as power plane.

• Locally bypass MXEVDD with 0.1 μF and 0.01 μF decou-

pling capacitors to MXEGND.

• Avoid routing other switching signals near to MXEVDD to

avoid crosstalk.

Rev. A | Page 19 of 60 | February 2008

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