ADSP-BF539F(RevA) Просмотр технического описания (PDF) - Analog Devices
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ADSP-BF539F Datasheet PDF : 60 Pages
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ADSP-BF539/ADSP-BF539F
layout. The resistor value depends on the drive level specified by
the crystal manufacturer. System designs should verify the cus-
tomized values based on careful investigation on multiple
devices over the allowed temperature range.
A third-overtone crystal can be used at frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in Figure 7.
CLKOUT
EN
Blackfin
TO PLL CIRCUITRY
CLKIN
18pF*
XTAL
FOR OVERTONE
OPERATION ONLY
18pF*
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
Figure 7. External Crystal Connections
As shown in Figure 8, the core clock (CCLK) and system
peripheral clock (SCLK) are derived from the input clock
(CLKIN) signal. An on-chip PLL is capable of multiplying the
CLKIN signal by a user programmable 0.5× to 64× multiplica-
tion factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10×, but it can be
modified by a software instruction sequence. On-the-fly fre-
quency changes can be effected by simply writing to the
PLL_DIV register.
“FI NE” ADJUSTMENT
REQUI RES PLL SEQUENCING
“COARSE” ADJUSTMENT
ON-THE -FLY
CLKI N
P LL
0.5× TO 64×
VCO
÷ 1, 2, 4, 8
÷ 1:15
CCLK
SCLK
SCLK ≤ CCLK
SCLK ≤ 133MHz
Figure 8. Frequency Modification Methods
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 7 illustrates typical system clock ratios.
Table 7. Example System Clock Ratios
Signal Name Divider Ratio Example Frequency Ratios (MHz)
SSEL3–0
VCO/SCLK VCO
SCLK
0001
1:1
100
100
0110
6:1
300
50
1010
10:1
500
50
The maximum frequency of the system clock is fSCLK. Note that
the divisor ratio must be chosen to limit the system clock fre-
quency to its maximum of fSCLK. The SSEL value can be changed
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
Note that when the SSEL value is changed, it will affect all the
peripherals that derive their clock signals from the SCLK signal.
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 8. This programmable core clock capability is useful for
fast core frequency modifications.
Table 8. Core Clock Ratios
Signal Name
CSEL1–0
00
01
10
11
Divider Ratio
VCO/CCLK
1:1
2:1
4:1
8:1
Example Frequency Ratios
VCO
CCLK
300
300
300
150
500
125
200
25
BOOTING MODES
The ADSP-BF539/ADSP-BF539F processors have three mecha-
nisms (listed in Table 9) for automatically loading internal L1
instruction memory after a reset. A fourth mode is provided to
execute from external memory, bypassing the boot sequence.
Table 9. Booting Modes
BMODE1–0 Description
00
Execute from 16-bit external memory
(bypass boot ROM)
01
Boot from 8-bit or 16-bit flash or boot from on-chip
flash (ADSP-BF539F only)
10
Boot from SPI serial master connected to SPI0
11
Boot from SPI serial slave EEPROM /flash
(8-,16-, or 24-bit address range, or Atmel
AT45DB041, AT45DB081, or AT45DB161serial flash)
connected to SPI0
Rev. A | Page 16 of 60 | February 2008
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