Z80182_ Просмотр технического описания (PDF) - Zilog

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Компоненты Описание

производитель

Z80182_

Family MPU

Zilog 

Z8018x Family

MPU User Manual

297

Table 57. Internal I/O Registers (Continued)

Register

CSI/O Transmit/

Receive Data Register:

Timer Data Register

Channel 0L:

Timer Data Register

Channel 0H:

Timer Reload Register

Channel 0L:

Timer Reload Register

Channel 0H:

Timer Control Register

Channel 0L:

Mnemonics Address

TRDR

0B

Remarks

TMDR0L

0C

TMDR0H

0D

RLDR0L

0E

RLDR0H

0F

TCR

10

TF1 TF0

TE1 TE0 TOC1 TOC0 TDE1 TDE0

bit

during RESET

0

0

0

0

0

0

0

0

R/W

R

R

R/W R/W R/W

R/W R/W R/W

Timer Down

Count Enable 1,0

Timer Output Control 1,0

Timer Interrupt Enable 1,0

Timer Interrupt Flag 1,0

TOC1,0

00

01

10

11

A18/TOUT

Inhibited

Toggle

0

1

UM005001-ZMP0400

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