Z80182_ Просмотр технического описания (PDF) - Zilog
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Z80182_ Datasheet PDF : 326 Pages
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Z8018x Family
MPU User Manual
296
Table 57. Internal I/O Registers (Continued)
Register
Mnemonics Address
Remarks
ASCI Transmit Data
Register Channel 0:
TDR0
06
ASCI Transmit Data
Register Channel 1:
TDR1
07
ASCI Receive Data
Register Channel 0:
TSR0
08
ASCI Receive Data
Register Channel 1:
TSR1
09
CSI/O Control Register: CNTR
0A
bit
EF
EIE RE
TE
—
SS2 SS1 SS0
during RESET 0
R/W
R
0
0
0
1
R/W R/W R/W
1
R/W
1
R/W
1
R/W
Speed Select
Transmit Enable
Receive Enable
End Interrupt Enable
End Flag
SS2 1 0
000
001
010
011
Baud Rate
Phi ÷
20
÷
40
÷
80
÷ 160
SS2 1 0
100
101
110
111
Baud Rate
Phi ÷
÷
÷
320
640
1280
External
frequency < ÷ 20)
UM005001-ZMP0400
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