Z80182_ Просмотр технического описания (PDF) - Zilog

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Компоненты Описание

производитель

Z80182_

Family MPU

Zilog 

Z8018x Family

MPU User Manual

295

Table 57. Internal I/O Registers (Continued)

Register

ASCI Status Channel 0:

ASCI Status Channel 1:

Mnemonics Address

Remarks

STAT0

STAT1

0

4

RDRF OVRN PE

FE RIE DCD0 TDRE TIE

bit

during RESET

0

0

0

0 invalid *

**

0

R/W

R

R

R

R R/W

R

R R/W

Transmit Interrupt Enable

Transmit Data Register Empty

Data Carrier Detect

Receive Interrupt Enable

Framing Error

Parity Error

Overrun Error

Receive Data Register Full

** CTS0 Pin TDRE

L

1

* DCD0: Depending on the condition of DCD0 Pin.

H

0

05

bit

during RESET

R/W

RDRF OVRN PE

FE

RIE CTS1E TDRE TIE

0

0

0

00

0

1

0

R

R

R

R R/W

R

R R/W

Transmit Interrupt Enable

Transmit Data Register Empty

CTS1 Enable

Receive Interrupt Enable

Framing Error

Parity Error

Overrun Error

Receive Data Register Full

UM005001-ZMP0400

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