DSP56F826PB Просмотр технического описания (PDF) - Motorola => Freescale

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DSP56F826PB

16-bit Hybrid Controller

Motorola => Freescale 

Freescale Semiconductor, Inc.

Table 7. DC Electrical Characteristics (Continued)

Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz

Characteristic

Symbol

Min

Typ Max Unit

PWM pin output sink current4

IOLP

16

—

—

mA

Input capacitance

CIN

—

8

—

pF

Output capacitance

COUT

—

12

—

pF

VDD supply current

IDDT5

Run 6

—

47

75

mA

Wait7

—

21

36

mA

Stop

—

2

8

mA

Low Voltage Interrupt, VDDIO power supply8

VEIO

2.4

2.7

3.0

V

Low Voltage Interrupt, VDD power supply9

VEIC

2.0

2.2

2.4

V

Power on Reset10

VPOR

—

1.7

2.0

V

1. Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, TCS, TCK, TRST, TMS, TDI and RXD1

2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.

3. PWM pin output source current measured with 50% duty cycle.

4. PWM pin output sink current measured with 50% duty cycle.

5. IDDT = IDD + IDDA (Total supply current for VDD + VDDA)

6. Run (operating) IDD measured using 4MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports

configured as inputs; measured with all modules enabled.

7. Wait IDD measured using external square wave clock source (fosc = 4MHz) into XTAL; all inputs 0.2V from rail; no DC

loads; less than 50pF on all outputs. CL = 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects

wait IDD; measured with PLL enabled.

8. This low-voltage interrupt monitors the VDDIO power supply. If VDDIO drops below VEIO, an interrupt is generated.

Functionality of the device is guaranteed under transient conditions when VDDIO >VEIO (between the minimum specified

VDDIO and the point when the VEIO interrupt is generated).

9. This low-voltage interrupt monitors theVDD power supply. If VDDIO drops below VEIC , an interrupt is generated.

Functionality of the device is guaranteed under transient conditions when VDD >VEIC (between the minimum specified VDD

and the point when the VEIC interrupt is generated).

10. Power–on reset occurs whenever the VDD power supply drops below VPOR. While power is ramping up, this signal

remains active for as long as VDD is below VPOR no matter how long the ramp-up rate is.

18

56F826 Technical Data

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