ADSP-21160M(Rev0) Просмотр технического описания (PDF) - Analog Devices
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ADSP-21160M Datasheet PDF : 52 Pages
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ADSP-21160M
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to
memories (and memory-mapped peripherals) without
reference to CLKIN. These specifications apply when the
ADSP-21160M is the bus master accessing external
memory space in asynchronous access mode. Note that
timing for ACK, DATA, RDx, WRx, and DMAG strobe
timing parameters only applies to asynchronous access
mode.
Table 10. Memory Write—Bus Master
Parameter
Min
Max
Unit
Timing Requirements:
tDAAK
ACK Delay from Address, Selects1,2
tDSAK
ACK Delay from WRx Low1,3
tSAKC
ACK Setup to CLKIN1,3
tHAKC
ACK Hold After CLKIN1,3
Switching Characteristics:
0.5tCCLK + 3
1
tCK – 0.5tCCLK–12+W
ns
tCK– 0.75tCCLK– 11+W ns
ns
ns
tDAWH
tDAWL
tWW
tDDWH
tDWHA
tDWHD
tDATRWH
tWWR
Address, CIF, Selects to WRx
tCK – 0.25tCCLK – 3+W
ns
Deasserted2,3
Address, CIF, Selects to WRx Low2
0.25tCCLK – 3
ns
WRx Pulse width3
tCK – 0.5tCCLK – 1+W
ns
Data Setup before WRx High3
tCK– 0.25tCCLK – 12.5+W
ns
Address Hold after WRx Deasserted3 0.25tCCLK – 1+H
ns
Data Hold after WRx Deasserted3
Data Disable after WRx Deasserted3,4
0.25tCCLK – 1+H
0.25tCCLK – 2+H
ns
0.25tCCLK+ 2 + H
ns
WRx High to WRx, RDx, DMAGx
0.5tCCLK – 1+HI
ns
Low3
tDDWR
Data Disable before WRx or RDx Low 0.25tCCLK – 1+I
ns
tWDE
WRx Low to Data Enabled
–0.25tCCLK – 1
ns
W = (number of wait states specified in WAIT register) × tCK.
H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
1ACK Delay/Setup: User must meet tDAAK or tDSAK or tSAKC for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).
2The falling edge of MSx, BMS is referenced.
3Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to asynchronous access mode.
4See Example System Hold Time Calculation on page 44 for calculation of hold times given capacitive and dc loads.
–20–
REV. 0
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