ADSP-21160M(Rev0) Просмотр технического описания (PDF) - Analog Devices

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ADSP-21160M
(Rev.:Rev0)

SHARC® DSP Microcomputer

Analog Devices 

ADSP-21160M

Memory Read—Bus Master

Use these specifications for asynchronous interfacing to

memories (and memory-mapped peripherals) without

reference to CLKIN. These specifications apply when the

ADSP-21160M is the bus master accessing external

memory space in asynchronous access mode. Note that

timing for ACK, DATA, RDx, WRx, and DMAG strobe

timing parameters only applies to asynchronous access

mode.

Table 9. Memory Read—Bus Master

Parameter

Min

Max

Unit

Timing Requirements:

tDAD

Address, CIF, Selects Delay to Data

Valid1,2

tDRLD

tHDA

tSDS

tHDRH

tDAAK

tDSAK

tSAKC

tHAKC

RDx Low to Data Valid1,3

Data Hold from Address, Selects4

Data Setup to RDx High1

Data Hold from RDx High3,4

ACK Delay from Address, Selects2,5

ACK Delay from RDx Low3,5

ACK Setup to CLKIN3,5

ACK Hold After CLKIN3

Switching Characteristics:

0

8

1

0.5tCCLK + 3

1

tCK – 0.25tCCLK– 11+W ns

0.75tCK – 11+W

ns

ns

ns

ns

tCK – 0.5tCCLK – 12+W

ns

tCK – 0.75tCCLK– 11+W ns

ns

ns

tDRHA

Address, CIF, Selects Hold After RDx 0.25tCCLK – 1+H

ns

High3

tDARL

Address, CIF, Selects to RDx Low2

0.25tCCLK – 3

ns

tRW

RDx Pulse width3

tCK – 0.5tCCLK – 1+W

ns

tRWR

RDx High to WRx, RDx, DMAGx Low3 0.5tCCLK – 1+HI

ns

W = (number of wait states specified in WAIT register) ؋ tCK.

HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).

1Data Delay/Setup: User must meet tDAD, tDRLD, or tSDS.

2The falling edge of MSx, BMS is referenced.

3Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to asynchronous access mode.

4Data Hold: User must meet tHDA or tHDRH in asynchronous access mode. See Example System Hold Time Calculation on page 44 for the calculation of

hold times given capacitive and dc loads.

5ACK Delay/Setup: User must meet tDAAK, tDSAK, or tSAKC for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).

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Figure 15. Memory Read—Bus Master

–19–

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