ADSP-21160M(Rev0) Просмотр технического описания (PDF) - Analog Devices

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ADSP-21160M
(Rev.:Rev0)

SHARC® DSP Microcomputer

Analog Devices 

ADSP-21160M

Clock Input

Table 4. Clock Input

Parameter

Timing Requirements:

tCK

CLKIN Period

tCKL

CLKIN Width Low

tCKH

CLKIN Width High

tCKRF

CLKIN Rise/Fall (0.4V–2.0V)

80 MHz

Min Max

Unit

25 80 ns

10.5 40 ns

10.5 40 ns

3

ns

&/.,1

W&.

W&.+

W&./

Figure 10. Clock Input

Reset

Table 5. Reset

Parameter

Min

Max

Unit

Timing Requirements:

tWRST

RESET Pulsewidth Low1

4tCK

ns

tSRST

RESET Setup Before CLKIN High2

8

ns

1Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 ms while RESET is

low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).

2Only required if multiple ADSP-21160Ms must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple

ADSP-21160Ms communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself

after reset.

&/.,1

5(6(7

W: 5 6 7

Figure 11. Reset

W6567

–16–

REV. 0

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