DS2153Q Просмотр технического описания (PDF) - Maxim Integrated

Номер в каталоге

Компоненты Описание

производитель

DS2153Q

E1 Single-Chip Transceiver

Maxim Integrated 

DS2153Q

1 DETAILED DESCRIPTION

The DS2153Q E1 single-chip transceiver (SCT) contains all the necessary functions for connection to E1

lines. The on-board clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ serial

stream. The DS2153Q automatically adjusts to E1 22 AWG (0.6mm) twisted-pair cables from 0 to 1.5km.

The device can generate the necessary G.703 waveshapes for both 75Ω and 120Ω cables. The on-board

jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data

paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It

is also used for extracting and inserting signaling data, Si, and Sa-bit information. The device contains a

set of 71 8-bit internal registers that the user can access to control the operation of the unit. Quick access

via the parallel control port allows a single micro to handle many E1 lines. The device fully meets all the

latest E1 specifications, including ITU G.703, G.704, G.706, G.823, and I.431 as well as ETSI 300 011,

300 233, TBR 12 and TBR 13.

1.1 Introduction

The analog AMI waveform off of the E1 line is transformer coupled into the RRING and RTIP pins of

the DS2153Q. The device recovers clock and data from the analog signal and passes it through the jitter

attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing

pattern. If needed, the receive side elastic store can be enabled in order to absorb the phase and frequency

differences between the recovered E1 data stream and an asynchronous backplane clock which is

provided at the SYSCLK input.

The transmit side of the DS2153Q is totally independent from the receive side in both the clock

requirements and characteristics. The transmit formatter will provide the necessary data overhead for E1

transmission. Once the data stream has been prepared for transmission, it is sent via the jitter attenuation

mux to the waveshaping and line driver functions. The DS2153Q will drive the E1 line from the TTIP

and TRING pins via a coupling transformer.

1.2 Reader’s Note

This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8-bit

time slots in E1 systems that are numbered 0 to 31. Time slot 0 is transmitted first and received first.

These 32 time slots are also referred to as channels with a numbering scheme of 1 to 32. Time slot 0 is

identical to channel 1, time slot 1 is identical to channel 2, and so on. Each time slot (or channel) is made

up of 8 bits numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB

and is transmitted last. Throughout this data sheet, the following abbreviations are used:

FAS

CAS

MF

Si

CRC4

CCS

Sa

E-bit

Frame Alignment Signal

Channel Associated Signaling

Multiframe

International Bits

Cyclical Redundancy Check

Common Channel Signaling

Additional bits

CRC4 Error bits

4 of 60

Share Link: