DS2153Q Просмотр технического описания (PDF) - Maxim Integrated

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Компоненты Описание

производитель

DS2153Q

E1 Single-Chip Transceiver

Maxim Integrated 

DS2153Q

PIN

20

21, 22

23

24

25, 26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

NAME

BTS

RTIP,

RRING

RVDD

RVSS

XTAL1,

XTAL2

INT1

INT2

TTIP

TVSS

TVDD

TRING

TCHBLK

TLCLK

TLINK

TSYNC

DVDD

TCLK

TSER

TCHCLK

TYPE

I

—

—

—

—

O

O

—

—

—

—

O

O

I

I/O

—

I

I

O

FUNCTION

Bus Type Select. Strap high to select Motorola bus timing; strap low to

select Intel bus timing. This pin controls the function of the RD (DS),

ALE(AS), and WR (R/ W ) pins. If BTS = 1, then these pins assume the

function listed in parentheses ().

Receive Tip and Ring. Analog inputs for clock recovery circuitry;

connects to a 1:1 transformer (see Section 13 for details).

Receive Analog Positive Supply. 5.0V. Should be tied to DVDD and

TVDD pins.

Receive Signal Ground. 0V. Should be tied to local ground plane.

Crystal Connections. A pullable 8.192MHz crystal must be applied to

these pins. See Section 13 for crystal specifications.

Receive Alarm Interrupt 1. Flags host controller during alarm

conditions defined in Status Register 1. Active low, open drain output.

Receive Alarm Interrupt 2. Flags host controller during conditions

defined in Status Register 2. Active low, open drain output.

Transmit Tip. Analog line driver output; connects to a step-up

transformer (see Section 13 for details).

Transmit Signal Ground. 0V. Should be tied to local ground plane.

Transmit Analog Positive Supply. 5.0V. Should be tied to DVDD and

RVDD pins.

Transmit Ring. Analog line driver outputs; connects to a step-up

transformer (see Section 13 for details).

Transmit Channel Block. A user-programmable output that can be

forced high or low during any of the 32 E1 channels. Useful for

blocking clocks to a serial UART or LAPD controller in applications

where not all E1 channels are used such as Fractional E1, 384kbps

service (H0), 1920kbps (H12), or ISDN-PRI. Also useful for locating

individual channels in drop-and-insert applications. See Section 14 for

timing details.

Transmit Link Clock. 4kHz to 20kHz demand clock for the TLINK

input. Controlled by TCR2. See Section 14 for timing details.

Transmit Link Data. If enabled, this pin will be sampled on the falling

edge of TCLK to insert the Sa bits. See Section 14 for timing details.

Transmit Sync. A pulse at this pin will establish either frame or

multiframe boundaries for the DS2153Q. Via TCR1.1, the DS2153Q

can be programmed to output either a frame or multiframe pulse at this

pin. See Section 14 for timing details.

Digital Positive Supply. 5.0V. Should be tied to RVDD and TVDD

pins.

Transmit Clock. 2.048MHz primary clock.

Transmit Serial Data. Transmit NRZ serial data, sampled on the

falling edge of TCLK.

Transmit Channel Clock. 256kHz clock that pulses high during the

LSB of each channel. Useful for parallel to serial conversion of channel

data. See Section 14 for timing details.

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