DS2153Q Просмотр технического описания (PDF) - Maxim Integrated
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DS2153Q Datasheet PDF : 60 Pages
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DS2153Q
E1 Single-Chip Transceiver
www.maxim-ic.com
FEATURES
Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceiver Functionality
On-Board Line Interface for Clock/Data
Recovery and Waveshaping
32-Bit or 128-Bit Jitter Attenuator
Generates Line Build-Outs for Both 120Ω
and 75Ω Lines
Frames to FAS, CAS, and CRC4 Formats
Dual On-Board Two-Frame Elastic Store Slip
Buffers That can Connect to Backplanes Up
to 8.192MHz
8-Bit Parallel Control Port That can be Used
on Either Multiplexed or Nonmultiplexed
Buses
Extracts and Inserts CAS Signaling
Detects and Generates Remote and AIS
Alarms
Programmable Output Clocks for Fractional
E1, H0, and H12 Applications
Fully Independent Transmit and Receive
Functionality
Full Access to Both Si and Sa Bits
Three Separate Loopbacks for Testing
Large Counters for Bipolar and Code
Violations, CRC4 Codeword Errors, FAS
Errors, and E Bits
Pin Compatible with DS2151Q T1 Single-
Chip Transceiver
5V Supply; Low-Power CMOS
ORDERING INFORMATION
PART
DS2153Q
DS2153Q+
DS2153QN
DS2153QN+
TEMP
RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
44 PLCC
44 PLCC
44 PLCC
44 PLCC
+Denotes lead-free/RoHS-compliant package.
PIN CONFIGURATION
FUNCTIONAL BLOCKS
PARALLEL CONTROL
PORT
Dallas
DS2153Q
T1SCT
ACTUAL SIZE OF 44-PIN PLCC
ALE(AS) 7
WR (R/W) 8
RLINK 9
RLCLK 10
DVSS
11
RCLK
12
RCHCLK 13
RSER 14
RSYNC 15
RLOS/LOTC 16
SYSCLK
17
DS2153Q
39
TSER
38
TCLK
37
DVDD
36 TSYNC
35 TLINK
34 TLCLK
33 TCHBLK
32 TRING
31
TVDD
30
TVSS
29
TTIP
PLCC
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 01106
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