N386SX Просмотр технического описания (PDF) - Intel

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N386SX

Intel387™ SX MATH COPROCESSOR

Intel 

Intel387TM SX MATH COPROCESSOR

1 1 Pin Description Table

The following table lists a brief description of each

pin on the Intel387 SX Math CoProcessor For a

more complete description refer to Section 4 1 Sig-

nal Description The following definitions are used in

these descriptions

The signal is active LOW

I

Input Signal

O Output Signal

I O Input and Output Signal

Symbol

ADS

BUSY

CKM

CMD0

CPUCLK2

D15 – D0

ERROR

NC

NPS1

NPS2

NUMCLK2

PEREQ

READY

READYO

RESETIN

STEN

WR

VCC

VSS

Type

I

O

I

I

I

IO

O

I

I

I

O

I

O

I

I

I

I

I

Name and Function

ADDRESS STROBE indicates that the address and bus cycle definition is valid

BUSY indicates that the Math CoProcessor is currently executing an instruction

CLOCKING MODE is used to select synchronous or asynchronous clock modes

COMMAND determines whether an opcode or operand are being sent to the Math

CoProcessor During a read cycle it indicates which register group is being read

CPU CLOCK input provides the timing for the bus interface unit and the execution

unit in synchronous mode

DATA BUS is used to transfer instructions and data between the Math

CoProcessor and CPU

ERROR signals that an unmasked exception has occurred

NO CONNECT should always remain unconnected Connection of a N C pin may

cause the Math CoProcessor to malfunction or be incompatible with future

steppings

NPX SELECT 1 is used to select the Math CoProcessor

NPX SELECT 2 is used to select the Math CoProcessor

NUMERICS CLOCK is used in asynchronous mode to drive the Floating Point

Execution Unit

PROCESSOR EXTENSION REQUEST signals the CPU that the Math

CoProcessor is ready for data transfer to from its FIFO

READY indicates that the bus cycle is being terminated

READY OUT signals the CPU that the Math CoProcessor is terminating the bus

cycle

SYSTEM RESET terminates any operation in progress and forces the Math

CoProcessor to enter a dormant state

STATUS ENABLE serves as a master chip select for the Math CoProcessor

When inactive this pin forces all outputs and bi-directional pins into a floating

state

WRITE READ indicates whether the CPU bus cycle in progress is a read or a write

cycle

SYSTEM POWER provides the a5V nominal D C supply input

SYSTEM GROUND provides the 0V connection from which all inputs and outputs

are measured

6

6

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