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N386SX

Intel387™ SX MATH COPROCESSOR

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Intel387TM SX MATH COPROCESSOR

APPENDIX B

COMPATIBILITY BETWEEN THE 80287

AND 8087 MATH COPROCESSOR

The 80286 80287 operating in Real Address mode will execute 8086 8087 programs without major modifica-

tion However because of differences in the handling of numeric exceptions by the 80287 Math CoProcessor

and the 8087 Math CoProcessor exception handling routines may need to be changed This appendix summa-

rizes the differences between the 80287 Math CoProcessor and the 8087 Math CoProcessor and provides

details showing how 8087 8087 programs can be ported to the 80286 80287

1 The Math CoProcessor signals exceptions through a dedicated ERROR line to the 80286 The Math

CoProcessor error signal does not pass through an interrupt controller (the 8087 INT signal does) There-

fore any interrupt controller oriented instructions in numeric exception handlers for the 8086 8087 should

be deleted

2 The 8087 instructions FENI and FDISI perform no useful function in the 80287 If the 80287 encounters one

of these opcodes in its instruction stream the instruction will effectively be ignored none of the 80287

internal states will be updated While 8086 8087 programs containing the instruction may be executed on

the 80286 80287 it is unlikely that the exception handling routines containing these instructions will be

completely portable to the 80287

3 Interrupt vector 16 must point to the numeric exception handling routine

4 The ESC instruction address saved in the 80287 includes any leading prefixes before the ESC opcode The

corresponding address saved in the 8087 does not include leading prefixes

5 In Protected Address mode the format of the 80287’s saved instruction and address pointers is different

than for the 8087 The instruction opcode is not saved in Protected mode exception handlers will have to

retrieve the opcode from memory if needed

6 Interrupt 7 will occur in the 80286 when executing ESC instructions with either TS (task switched) or EM

(emulation) of the 80286 MSW set (TS e 1 or EM e 1) It TS is set then a WAIT instruction will also cause

interrupt 7 An exception handler should be included in 80286 80287 code to handle these situations

7 Interrupt 9 will occur if the second or subsequent words of a floating point operand fall outside a segment’s

size Interrupt 13 will occur if the starting address of a numeric operand falls outside a segment’s size An

exception handler should be included in 80286 80287 code to report these programming errors

8 Except for the processor control instructions all of the 80287 numeric instructions are automatically syn-

chronized by the 80286 CPU the 80286 CPU automatically tests the BUSY line from the 80287 to ensure

that the 80287 has completed its previous instruction before executing the next ESC instruction No explicit

WAIT instructions are required to assure this synchronization For the 8087 used witth 8086 and 8088

processors explicit WAITs are required before each numeric instruction to ensure synchronization Al-

though 8086 8087 programs having explicit WAIT instructions will execute perfectly on the 80286 80287

without reassembly these WAIT instructions are unnecessary

9 Since the 80287 does not require WAIT instructions before each numeric instruction the ASM286 assem-

bler does not automatically generate these WAIT instuctions The ASM86 assembler however automati-

cally precedes every ESC instruction with a WAIT instruction Although numeric routines generated using

the ASM86 assembler will generally execute correctly on the 80286 80287 reassembly using ASM286

may result in a more compact code image

The processor control instructions for the 80287 may be coded using either a WAIT or No-WAIT form of

mnemonic The WAIT forms of these instructions cause ASM286 to precede the ESC instructions with a CPU

WAIT instruction in the identical manner as does ASM86

B-1

47

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