AS5SS256K36 Просмотр технического описания (PDF) - Micross Components
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AS5SS256K36 Datasheet PDF : 17 Pages
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SSRAM
AS5SS256K36
PIN DESCRIPTION
Pin Number
37
36
32-35, 44-50,
81, 82, 99,
100
43
93
94
95
96
87
88
89
98
92
SYMBOL TYPE
DESCRIPTION
SA0
Synchronous Address Inputs: These inputs are registered and must meet
SA1 Input the setup and hold times around the rising edge of CLK. Two different
SA
pinouts are available for the TQFP packages.
BWa\
BWb\
BWc\
BWd\
BWE\
GW\
CLK
CE\
CE2\
Input
Input
Input
Input
Input
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold times
around the rising edge of CLK. A byte write enable is LOW for a WRITE
cycle and HIGH for a READ cycle. Bwa\ controls DQa pins and DQPa;
Bwb\ controls DQb pins and DQPb; Bwc\ controls DQc pins and DQPc;
Bwd\ controls DQd pins and DQPd. Parity bits are featured on this
device.
Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold items around the rising
edge of CLK.
Global Write: This active LOW input allows a full 36-bit WRITE to occur
independent of the BWE\ and BWx\ lines and must meet the setup and
hold times around the rising edge of CLK.
Clock: CLK registers address, data, chip enable, byte write enables and
burst control inputs on its rising edge. All synchronous inputs must meet
setup and hold times around the clock's rising edge.
Synchronous Chip Enable: This active LOW input is used to enable the
device and conditions the internal use of ADSP\. CE\ is sampled only
when a new external address is loaded.
Input
Synchronous Chip Enable: This active LOW input is used to enable the
device and is sampled only when a new external address is loaded.
97
CE2
Input
Synchronous Chip Enable: This active HIGH input is used to enable the
device and is sampled only when a new external address is loaded.
86
OE\
Input
Output Enable: This active LOW, asynchronous input enables the data
I/O output drivers.
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after the
83
ADV\
Input
external address is loaded. A HIGH on this pin effectively causes wait
states to be generated (no address advance). To ensure use of correct
address during a WRITE cycle, ADV\ must be HIGH at the rising edge of
the first clock after an ADSP\ cycle is initiated.
Synchronous Address Status Controller: This active LOW input interrupts
any ongoing burst, causing a new external address to be registered. A
85
ADSC\ Input READ or WRITE is performed using the new address if CE\ is LOW.
ADSC\ is also used to place the chip into power-down state when CE\ is
HIGH.
AS5SS256K36
Rev. 4.4 10/13
Micross Components reserves the right to change products or specifications without notice.
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