Pin
PB2/SCK0
PB5/SCK1
2 pins
PB4/SO0
PB7/SO1
2 pins
PC0 to PC7
8 pins
CXP83620/83624, CXP83621/83625
Port B
Pull-up resistor
"0" after a reset
Output buffer capability
"0" after a reset
SCK out
Serial clock output ebable
Port B function select
"0" after a reset
Port B data
Port B direction
"0" after a reset
Internal
data bus
RD (Port B)
SCK in
Port B
Pull-up resistor
"0" after a reset
Output buffer capability
"0" after a reset
SO
Serial data output ebable
Port B function select
"0" after a reset
Port B data
Port B direction
"0" after a reset
Internal
data bus
RD (Port B)
Port C
Pull-up resistor
"0" after a reset
Port C data
Circuit format
After a reset
∗
Schmitt input
IP
∗ Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
Hi-Z
∗
Hi-Z
IP
∗ Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
∗2
Port C direction
"0" after a reset
Internal data bus
RD (Port C)
∗1
IP
–9–
∗1 High current drive
12mA (VDD = 4.5 to 5.5V)
4.5mA (VDD = 2.7 to 3.3V)
∗2 Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
Hi-Z