I/O Circuit Format for Pins
Pin
Port A
Pull-up resistor
"0" after a reset
Port A data
Circuit format
CXP83620/83624, CXP83621/83625
After a reset
∗
PA0/AN0
to
PA7/AN7
8 pins
PB0
1 pin
PB1/CS0
PB3/SI0
PB6/SI1
3 pins
Port A direction
"0" after a reset
Internal data bus
RD (Port A)
Port A function select
"0" after a reset
Standby release
IP
Input protection
circuit
Edge detection
circuit
Input multiplexer
A/D converter
∗ Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
Port B
Pull-up resistor
∗
"0" after a reset
Port B data
Port B direction
"0" after a reset
Internal data bus
RD (Port B)
Port B
Pull-up resistor
"0" after a reset
Port B data
IP
∗ Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
∗
Port B direction
"0" after a reset
Internal data bus
RD (Port B)
CS0
SI0
SI1
–8–
IP
Schmitt input
∗ Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
Hi-Z
Hi-Z
Hi-Z