CXP83620/83624, CXP83621/83625
Pin
PE0/INT0/EC
PE1/INT1
PE2/INT2
PE3/INT3
PE4/RMC
5 pins
Port E
Circuit format
Schmitt input
IP
INT0/EC
INT1
INT2
INT3
RMC
Internal data bus
RD (Port E)
After a reset
Hi-Z
PE5/TO
1 pin
Port E
TO
Port E function select
"0" after a reset
Port E data
"1" after a reset
Internal data bus
RD (Port E)
High level
PE6/ADJ
1 pin
Port E
Internal reset signal
∗2
Port E data
"1" after a reset
∗1 ADJ32K
ADJ16K
ADJ2K
00
MPX
01
10
11
Port E function select (upper)
Port E function select (lower)
"00" after a reset
Internal data bus
RD (Port E)
∗1 ADJ signals are frequency driver
outputs for TEX oscillation frequency
adjustment.
ADJ2K provides usage as buzzer output.
∗2 Pull-up transistor
approx. 150kΩ (VDD = 4.5 to 5.5V)
approx. 200kΩ (VDD = 2.7 to 3.3V)
High level
High level
at ON
resistance
of pull-up
transistor
during a
reset.
PH0/INT4
1 pin
Port H
Pull-up resistor
∗
"0" after a reset
Port H data
Port H direction
"0" after a reset
Internal data bus
RD (Port H)
INT4
– 10 –
IP
Schmitt input
∗ Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)
Hi-Z