CDB8952 Просмотр технического описания (PDF) - Cirrus Logic
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CDB8952 Datasheet PDF : 86 Pages
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CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
AN[1:0] - Auto-Negotiate Control. Input, Pins 58 and 57.
These three-level input pins are sampled during power-up or reset. They control the forced or
advertised auto-negotiation operating modes. If either of these pins is left unconnected, internal
logic pulls its signal to a mid-range value, designated as 'M' in the following table. Either pin
may also be connected to a 5 to 25 MHz TTL-level clock source, designated as ’C’ in the
following table. A minimum of 8 rising edges of the clock are required while RESET is
asserted for the AN[1:0] input logic to interpret the input as ’C’.
AN1 pin
0
1
M
M
C
M
C
M
0
0
1
1
C
C
1
0
AN0 pin
M
M
0
1
M
C
C
M
0
1
0
1
1
0
C
C
Forced/Auto
Forced
Forced
Forced
Forced
Forced
Forced
Forced
Auto-Neg
Auto-Neg
Auto-Neg
Auto-Neg
Auto-Neg
Auto-Neg
Auto-Neg
Auto-Neg
Auto-Neg
Speed
10 Mb/s
10 Mb/s
100 Mb/s
100 Mb/s
100 Mb/s
100 Mb/s
100 Mb/s
100/10 Mb/s
10 Mb/s
10 Mb/s
100 Mb/s
100 Mb/s
100/10 Mb/s
100/10 Mb/s
100 Mb/s
10 Mb/s
Full/Half Duplex
Half
Full
Half
Full
Full (Note 1)
Full (Note 2)
Half (Note 3)
Full/Half
Half
Full
Half
Full
Full
Half
Full/Half
Full/Half
1. The Auto-Negotiation Advertisement Register will be modified to advertise 100 Mb/s
Full/Half.
2. The Auto-Negotiation Advertisement Register will be modified to advertise
100/10 Mb/s Full.
3. The Auto-Negotiation Advertisement Register will be modified to advertise
100/10 Mb/s Half.
Auto-Negotiation may also be enabled and the advertised capabilities modified under software
control through bit 8 of the Basic Mode Control Register (address 00h), and bits 5, 6, 7, 8, and
10 of the Auto-Negotiation Advertisement Register (address 04h).
These pins are pulled to ‘M’ through weak internal resistors (> 150 KΩ). Other values may be
set by tying them directly to VDD_MII, VSS, or a clock source, or through external 10 KΩ
pull-up or pull-down resistors.
BP4B5B - Bypass 4B5B Coders. Input, Pin 56.
When driven high during power-up or reset, the transmit 4B5B encoder and receiver 5B4B
decoder are bypassed. Five-bit code groups are output and input on pins RXD[4:0] and
TXD[4:0].
The 4B5B Coders may also be bypassed under software control through bit 14 of the
Loopback, Bypass, and Receiver Error Mask Register (address 18h).
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
DS206TPP2
11
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