CDB8952 Просмотр технического описания (PDF) - Cirrus Logic

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CDB8952

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

Cirrus Logic 

CS8952T

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

At power-up or at reset, the value on this pin is latched into bit 14 of the Loopback, Bypass

and Receiver Error Mask Register (address 18h). This pin includes a weak internal pull-down

(> 20 KΩ), or the value may be set by an external 4.7 KΩ pull-up or pull-down resistor.

BPALIGN - Bypass Symbol Alignment. Input, Pin 52.

When driven high during power-up or reset, the following blocks are bypassed: 4B5B encoder,

5B4B decoder, scrambler and descrambler. Five-bit code groups are output and input on pins

RXD[4:0] and TXD[4:0]. The receiver will output five-bit data with no attempt to identify

code-group boundaries; therefore, the data in one RXD[4:0] word may contain data from two

code groups.

Symbol alignment may also be bypassed under software control through bit 12 of the

Loopback, Bypass, and Receiver Error Mask Register (address 18h).

At power-up or at reset, the value on this pin is latched into bit 12 of the Loopback, Bypass

and Receiver Error Mask Register (address 18h). This pin includes a weak internal pull-down

(> 20 KΩ), or the value may be set by an external 4.7 KΩ pull-up or pull-down resistor.

ISODEF - Isolate Default. Input, Pin 63.

When asserted high during power-up or reset, the MII will power-up electrically isolated except

for the MDIO and MDC pins. When low, the part will exit reset fully electrically connected to

the MII.

The MII may also be isolated under software control through bit 10 of the Basic Mode Control

Register (address 00h).

At power-up or at reset, the value on this pin is latched into bit 10 of the Basic Mode Control

Register (address 00h). This pin includes a weak internal pull-down (> 20 KΩ), or the value

may be set by an external 4.7 KΩ pull-up or pull-down resistor.

LED1 - Transmit Active LED. Open Drain Output, Pin 69.

This active-low output indicates transmit activity. It contains a pulse stretcher to insure that the

transmit events are visible when the pin is used to drive an LED. The definition of this pin may

be modified to indicate Disconnect Detection (bit 5 of the Self Status Register (address 19h))

by setting bit 2 of the PCS Sub-layer Configuration Register (address 17h).

This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input

pin.

LED2 - Receive Activity LED. Open Drain Output, Pin 70.

This active-low output indicates receive activity. It contains a pulse stretcher to insure that the

receive events are visible when the pin is used to drive an LED.

This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input

pin.

CIRRUS LOGIC ADVANCED PRODUCT DATABOOK

12

DS206TPP2

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