AT91SAM9G45(2009) Просмотр технического описания (PDF) - Atmel Corporation

Номер в каталоге

Компоненты Описание

производитель

AT91SAM9G45
(Rev.:2009)

AT91 ARM Thumb-based Microcontrollers

Atmel Corporation 

The control of these delays is the following:

• DDR2SDRC

DDR_D[15:0] controlled by 2 registers, DELAY1 and DELAY2, located in the DDR2SDRC user

interface

– DDR_D[0] <=> DELAY1[3:0],

– DDR_D[1] <=> DELAY1[7:4],...

– DDR_D[6] <=> DELAY1[27:24],

– DDR_D[7] <=> DELAY1[31:28]

– DDR_D[8] <=> DELAY2[3:0],

– DDR_D[9] <=> DELAY2[7:4],...,

– DDR_D[14] <=> DELAY2[27:24],

– DDR_D[15] <=> DELAY2[31:28]

DDR_A[13:0] controlled by 2 registers, DELAY3 and DELAY4, located in the DDR2SDRC user

interface

– DDR_A[0] <=> DELAY3[3:0],

– DDR_A[1] <=> DELAY3[7:4], ...,

– DDR_A[6] <=> DELAY3[27:24],

– DDR_A[7] <=> DELAY3[31:28]

– DDR_A[8] <=> DELAY4[3:0],

– DDR_A[9] <=> DELAY4[7:4], ...,

– DDR_A[12] <=> DELAY4[19:16],

– DDR_A[13] <=> DELAY4[23:20]

• EBI (DDR2SDRC\HSMC3\Nandflash)

D[15:0] controlled by 2 registers, DELAY1 and DELAY2, located in the HSMC3 user interface

– D[0] <=> DELAY1[3:0],

– D[1] <=> DELAY1[7:4],...,

– D[6] <=> DELAY1[27:24],

– D[7] <=> DELAY1[31:28]

– D[8] <=> DELAY2[3:0],

– D[9] <=> DELAY2[7:4],...,

– D[14] <=> DELAY2[27:24],

– D[15] <=> DELAY2[31:28]

D[31,16]on PIOC[31:16] controlled by 2 registers, DELAY3 and DELAY4, located in the

HSMC3 user interface

– D[16] <=> DELAY3[3:0],

– D[17] <=> DELAY3[7:4],...,

– D[22] <=> DELAY3[27:24],

– PC[23] <=> DELAY3[31:28]

18 AT91SAM9G45

6438D–ATARM–13-Oct-09

Share Link: