AT91SAM9G45(2009) Просмотр технического описания (PDF) - Atmel Corporation

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AT91SAM9G45
(Rev.:2009)

AT91 ARM Thumb-based Microcontrollers

Atmel Corporation 

AT91SAM9G45

6.2.2

TCM Interface

On the processor side, this Internal SRAM can be allocated to two areas.

• Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block

anywhere in the ARM926 instruction memory space using CP15 instructions and the TCR

configuration register located in the Chip Configuration User Interface. This SRAM block is

also accessible by the ARM926 Masters and by the AHB Masters through the AHB bus

• Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block

anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is

also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus.

• Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap

Command is performed, this SRAM block is accessible through the AHB bus at address

0x0030 0000 by all the AHB Masters. After Remap, this SRAM block also becomes

accessible through the AHB bus at address 0x0 by the ARM926 Instruction and the ARM926

Data Masters.

Within the 64 Kbyte SRAM size available, the amount of memory assigned to each block is soft-

ware programmable according to Table 6-1.

Table 6-1. ITCM and DTCM Memory Configuration

SRAM A ITCM size (KBytes)

seen at 0x100000 through AHB

SRAM B DTCM size (KBytes)

seen at 0x200000 through AHB

0

0

0

64

32

32

SRAM C (KBytes)

seen at 0x300000 through AHB

64

0

0

6.2.3

Internal ROM

The AT91SAM9G45 embeds an Internal ROM, which contains the boot ROM and SAM-BA®

program.

At any time, the ROM is mapped at address 0x0040 0000. It is also accessible at address 0x0

(BMS =1) after the reset and before the Remap Command.

6.3 I/O Drive Selection and Delay Control

6.3.1

I/O Drive Selection

The aim of this control is to adapt the signal drive to the frequency. Two bits allow the user to

select High or Low drive for memories data/address/ctrl signals.

• Setting the bit [17], EBI_DRIVE, in the EBI_CSA register of the matrix allows to control the

drive of the EBI.

• Setting the bit [18], DDR_DRIVE, in the EBI_CSA register of the matrix allows to control the

drive of the DDR.

6.3.2

Delay Control

To avoid the simultaneous switching of all the I/Os, a delay can be inserted on the different EBI,

DDR2 and PIO lines.

17

6438D–ATARM–13-Oct-09

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