CY7C1061DV33(2006) Просмотр технического описания (PDF) - Cypress Semiconductor
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Компоненты Описание
производитель
CY7C1061DV33 Datasheet PDF : 10 Pages
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PRELIMINARY
CY7C1061DV33
Truth Table
CE1 CE2 OE WE BLE
HX XX X
X L XX X
L H LH L
L H LH L
L H LH H
LHXL L
LHXL L
LHXL H
L H HH X
BHE I/O0–I/O7
X High-Z
X High-Z
L Data Out
H Data Out
L High-Z
L Data In
H Data In
L High-Z
X High-Z
I/O8–I/O15
High-Z
High-Z
Data Out
High-Z
Data Out
Data In
High-Z
Data In
High-Z
Mode
Power-down
Power-down
Read All Bits
Read Lower Bits Only
Read Upper Bits Only
Write All Bits
Write Lower Bits Only
Write Upper Bits Only
Selected, Outputs Disabled
Power
Standby (ISB)
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Ordering Information
Speed
(ns)
10
Ordering Code
CY7C1061DV33-10ZXI
CY7C1061DV33-10BVXI
Package
Diagram
Package Type
51-85160 54-pin TSOP II (Pb-Free)
51-85178 48-ball Very Fine Pitch Ball Grid Array (8 × 9.5 × 1 mm) (Pb-Free)
Operating
Range
Industrial
Package Diagrams
54-pin TSOP Type II (51-85160)
Document #: 38-05476 Rev. *C
51-85160-**
Page 8 of 10
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