MK2049-35 Просмотр технического описания (PDF) - Integrated Circuit Systems
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MK2049-35 Datasheet PDF : 10 Pages
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MK2049-35
3.3 V Communications Clock PLL
MK2049-35 Output Decoding Table – External Mode (MHz)
ICLK FS3 FS2 FS1 FS0 CLK/2 CLK
8K
Crystal
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
0 0 0 0 1.544 3.088 8 kHz
0 0 0 1 2.048 4.096 8 kHz
0 0 1 0 22.368 44.736 8 kHz
0 0 1 1 17.184 34.368 8 kHz
0 1 0 0 19.44 38.88 8 kHz
0 1 0 1 12.8
25.6 8 kHz
0 1 1 0 25.92 51.84 8 kHz
0 1 1 1 4.096 8.192 8 kHz
1 0 0 0 18.528 37.056 8 kHz
1 0 0 1 12.352 24.704 8 kHz
1 0 1 0 24.576 49.152 8 kHz
1 0 1 1 16.384 32.768 8 kHz
1 1 0 0 17.28 34.56 8 kHz
1 1 0 1 62.5
125 8 kHz
24.576
24.576
24.576
24.576
19.44
25.6
17.28
16.384
24.704
24.704
16.384
16.384
17.28
25
MK2049-35 Output Decoding Table – Buffer Mode (MHz)
ICLK FS3 FS2 FS1 FS0 CLK/2 CLK
8K
20 - 50
10 - 25
1 1 1 0 ICLK 2*ICLK N/A
1 1 1 1 ICLK/2 ICLK N/A
Crystal
ICLK/2
ICLK
• 0 = connect directly to ground, 1 = connect directly to VDD.
• Crystal is connected to pins 2 and 3; clock input is applied to pin 13.
MDS 2049-35 A
4
Revision 121300
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
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