MK2049-35 Просмотр технического описания (PDF) - Integrated Circuit Systems
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MK2049-35 Datasheet PDF : 10 Pages
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MK2049-35
3.3 V Communications Clock PLL
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, VDD
Referenced to GND
Inputs and Clock Outputs
Ambient Operating Temperature
MK2049-34SI
Soldering Temperature
Max of 10 seconds
Storage Temperature
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
Operating Voltage, VDD
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH, CMOS level
IOH=-4 mA
Output High Voltage, VOH
IOH=-8 mA
Output Low Voltage
IOL=8 mA
Operating Supply Current, IDD
No Load, VDD=3.3 V
Short Circuit Current
Each output
Input Capacitance, FS3:0
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
Input Frequency, External Mode
ICLK
Input Clock Pulse Width
Propagation Delay
ICLK to 8 kHz
Delay, CLK/2 after CLK
Output Clock Rise Time
0.8 to 2.0 V
Output Clock Fall Time
2.0 to 0.8 V
Output Clock Duty Cycle, High Time
At VDD/2, except 8k
Actual mean frequency error versus target
Any clock selection
Minimum
-0.5
-40
-65
3.15
2
VDD-0.4
2.4
10
40
Typical
3.3
15
±50
5
8.000
7
4
0
Maximum
7
VDD+0.5
85
250
150
3.45
0.8
0.4
2
2
60
0
Units
V
V
°C
°C
°C
V
V
V
V
V
V
mA
mA
pF
kHz
ns
ns
ns
ns
ns
%
ppm
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
MDS 2049-35 A
3
Revision 121300
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
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