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DSP1627
(Rev.:2000)

DSP1627 Digital Signal Processor

Agere -> LSI Corporation 

Data Sheet

March 2000

DSP1627 Digital Signal Processor

4 Hardware Architecture

The DSP1627 device is a 16-bit, fixed-point program-

mable digital signal processor (DSP). The DSP1627

consists of a DSP1600 core together with on-chip mem-

ory and peripherals. Added architectural features give

the DSP1627 high program efficiency for signal coding

applications.

4.1 DSP1627 Architectural Overview

Figure 3 shows a block diagram of the DSP1627. The fol-

lowing modules make up the DSP1627.

DSP1600 Core

The DSP1600 core is the heart of the DSP1627 chip. The

core contains data and address arithmetic units, and

control for on-chip memory and peripherals. The core

provides support for external memory wait-states and on-

chip, dual-port RAM and features vectored interrupts and

a trap mechanism.

Dual-Port RAM (DPRAM)

This module contains six banks of zero wait-state mem-

ory. Each bank consists of 1K 16-bit words and has sep-

arate address and data ports to the instruction/coefficient

and data memory spaces. A program can reference

memory from either space. The DSP1600 core automat-

ically performs the required multiplexing. If references to

both ports of a single bank are made simultaneously, the

DSP1600 core automatically inserts a wait-state and per-

forms the data port access first, followed by the instruc-

tion/coefficient port access.

A program can be downloaded from slow, off-chip mem-

ory into DPRAM, and then executed without wait-states.

DPRAM is also useful for improving convolution perfor-

mance in cases where the coefficients are adaptive.

Since DPRAM can be downloaded through the JTAG

port, full-speed remote in-circuit emulation is possible.

DPRAM can also be used for downloading self-test code

via the JTAG port.

Read-Only Memory (ROM)

The DSP1627x36 contains 36K 16-bit words of zero

wait-state mask-programmable ROM for program and

fixed coefficients. Similarly, the DSP1627x32 has 32K

16-bit words of ROM and access to 16 Kwords of exter-

nal ROM.

External Memory Multiplexer (EMUX)

The EMUX is used to connect the DSP1627 to external

memory and I/O devices. It supports read/write opera-

tions from/to instruction/coefficient memory (X memory

space) and data memory (Y memory space). The

DSP1600 core automatically controls the EMUX. Instruc-

Lucent Technologies Inc.

tions can transparently reference external memory from

either set of internal buses. A sequencer allows a single

instruction to access both the X and the Y external mem-

ory spaces.

Clock Synthesis

The DSP powers up with a 1X input clock (CKI/CKI2) as

the source for the processor clock. An on-chip clock syn-

thesizer (PLL) can also be used to generate the system

clock for the DSP, which will run at a frequency multiple

of the input clock. The clock synthesizer is deselected

and powered down on reset. For low-power operation, an

internally generated slow clock can be used to drive the

DSP. If both the clock synthesizer and the internally gen-

erated slow clock are selected, the slow clock will drive

the DSP; however, the synthesizer will continue to run.

The clock synthesizer and other programmable clock

sources are discussed in Section 4.12. The use of these

programmable clock sources for power management is

discussed in Section 4.13.

Bit Manipulation Unit (BMU)

The BMU extends the DSP1600 core instruction set to

provide more efficient bit operations on accumulators.

The BMU contains logic for barrel shifting, normalization,

and bit field insertion/extraction. The unit also contains a

set of 36-bit alternate accumulators. The data in the al-

ternate accumulators can be shuffled with the data in the

main accumulators. Flags returned by the BMU mesh

seamlessly with the DSP1600 conditional instructions.

Bit Input/Output (BIO)

The BIO provides convenient and efficient monitoring

and control of eight individually configurable pins. When

configured as outputs, the pins can be individually set,

cleared, or toggled. When configured as inputs, individu-

al pins or combinations of pins can be tested for patterns.

Flags returned by the BIO mesh seamlessly with condi-

tional instructions.

Serial Input/Output Units (SIO and SIO2)

SIO and SIO2 offer asynchronous, full-duplex, double-

buffered channels that operate at up to 25 Mbits/s (for

20 ns instruction cycle in a nonmultiprocessor configura-

tion), and easily interface with other Lucent Technologies

fixed-point DSPs in a multiple-processor environment.

Commercially available codecs and time-division multi-

plex (TDM) channels can be interfaced to the serial I/O

ports with few, if any, additional components. SIO2 is

identical to SIO.

An 8-bit serial protocol channel may be transmitted in ad-

dition to the address of the called processor in multipro-

cessor mode. This feature is useful for transmitting high-

level framing information or for error detection and cor-

rection. SIO2 and BIO are pin-multiplexed with the PHIF.

7

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