DSP1627(2000) Просмотр технического описания (PDF) - Agere -> LSI Corporation
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DSP1627 Datasheet PDF : 154 Pages
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Data Sheet
March 2000
DSP1627 Digital Signal Processor
3 Pin Information (continued)
Functional descriptions of pins 1—100 are found in Section 6, Signal Descriptions. The functionality of pins 61 and
62 (TQFP pins 48 and 49) are mask-programmable (see Section 7, Mask-Programmable Options). Input levels on
all I and I/O type pins are designed to remain at full CMOS levels when not driven by the DSP.
Table 1. Pin Descriptions
BQFP Pin TQFP Pin
1, 2, 3, 4, 88, 89, 90,
5, 7, 8, 9, 91, 92, 94,
10, 11, 12, 95, 96, 97,
15, 16, 17, 98, 99, 2,
18, 19 3, 4, 5, 6
20
7
21
8
23
10
24
11
25
12
27
14
28, 29, 31, 15, 16, 18,
32, 33, 34, 19, 20, 21,
35, 36, 37, 22, 23, 24,
40, 41, 42, 27, 28, 29,
43, 44, 45, 30, 31, 32,
46
33
47
34
48
35
50
37
51
38
52
39
53
40
54
41
56
43
57
44
58
45
59
46
61
48
62
49
65
52
66
53
67
54
68
55
Symbol
DB[15:0]
IO
ERAMHI
ERAMLO
EROM
RWN
EXM
AB[15:0]
INT1
INT0
IACK
STOP
TRAP
RSTB
CKO
TCK
TMS
TDO
TDI
CKI**
CKI2**
VEC0/IOBIT7
VEC1/IOBIT6
VEC2/IOBIT5
VEC3/IOBIT4
Type
Name/Function
I/O* External Memory Data Bus DB[15:0].
O† Data Address 0x4000 to 0x40FF I/O Enable.
O† Data Address 0x8000 to 0xFFFF External RAM Enable.
O† Data Address 0x4100 to 0x7FFF External RAM Enable.
O† Program Address External ROM Enable.
O† Read/Write Not.
I External ROM Enable.
O* External Memory Address Bus 15—0.
I Vectored Interrupt 1.
I Vectored Interrupt 0.
O* Interrupt Acknowledge.
I STOP Input Clock.
I/O* Nonmaskable Program Trap/Breakpoint Indication.
I Reset Bar.
O† Processor Clock Output.
I JTAG Text Clock.
I‡ JTAG Test Mode Select.
O§ JTAG Test Data Output.
I‡ JTAG Test Data Input.
Mask-Programmable Input Clock Option
CMOS Small
Crystal
Signal
Oscillator
CMOS
I
CKI
VAC XLO, 10 pF capacitor to VSS CKI
I
VSSA
VCM XHI, 10 pF capacitor to VSS Open
I/O* Vectored Interrupt Indication 0/Status/Control Bit 7.
I/O* Vectored Interrupt Indication 1/Status/Control Bit 6.
I/O* Vectored Interrupt Indication 2/Status/Control Bit 5.
I/O* Vectored Interrupt Indication 3/Status/Control Bit 4.
* 3-states when RSTB = 0, or by JTAG control.
† 3-states when RSTB = 0 and INT0 = 1. Output = 1 when RSTB = 0 and INT0 = 0, except CKO which is free-running.
‡ Pull-up devices on input.
§ 3-states by JTAG control.
** See Section 7, Mask-Programmable Options.
†† For SIO multiprocessor applications, add 5 kΩ external pull-up resistors to SADD1 and/or SADD2 for proper initialization.
Lucent Technologies Inc.
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