DSP1627(2000) Просмотр технического описания (PDF) - Agere -> LSI Corporation
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DSP1627 Datasheet PDF : 154 Pages
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DSP1627 Digital Signal Processor
Data Sheet
March 2000
3 Pin Information (continued)
Functional descriptions of pins 1—100 are found in Section 6, Signal Descriptions.
Table 1. Pin Descriptions (continued)
BQFP Pin
69
70
71
72
74
75
77
78
79
80
81
82
83
84
85
86
87
90
91
92
93
94
95
96
98
99
6, 15, 26,
38, 49, 64,
76, 89, 97
14, 22, 30,
39, 55, 73,
88, 100
60
63
TQFP Pin
56
57
58
59
61
62
64
65
66
67
68
69
70
71
72
73
74
77
78
79
80
81
82
83
85
86
93, 1, 13,
25, 36, 51,
63, 76, 84
100, 9, 17,
26, 42, 60,
75, 87
47
50
Symbol
IOBIT3/PB7
IOBIT2/PB6
IOBIT1/PB5
IOBIT0/PB4
SADD2/PB3††
DOEN2/PB2
DI2/PB1
ICK2/PB0
OBE2/POBE
IBF2/PIBF
OLD2/PODS
ILD2/PIDS
SYNC2/PBSEL
DO2/PSTAT
OCK2/PCSN
DOEN1
SADD1††
SYNC1
DO1
OLD1
OCK1
ICK1
ILD1
DI1
IBF1
OBE1
VSS
VDD
VDDA
VSSA
Type
I/O*
I/O*
I/O*
I/O*
I/O*
I/O*
I/O*
I/O*
O*
O*
I/O*
I/O*
I/O*
I/O*
I/O*
I/O*
I/O*
I/O*
O*
I/O*
I/O*
I/O*
I/O*
I
O*
O*
P
P
P
P
Name/Function
Status/Control Bit 3/PHIF Data Bus Bit 7.
Status/Control Bit 2/PHIF Data Bus Bit 6.
Status/Control Bit 1/PHIF Data Bus Bit 5.
Status/Control Bit 0/PHIF Data Bus Bit 4.
SIO2 Multiprocessor Address/PHIF Data Bus Bit 3.
SIO2 Data Output Enable/PHIF Data Bus Bit 2.
SIO2 Data Input/PHIF Data Bus Bit 1.
SIO2 Input Clock/PHIF Data Bus Bit 0.
SIO2 Output Buffer Empty/PHIF Output Buffer Empty.
SIO2 Input Buffer Full/PHIF Input Buffer Full.
SIO2 Output Load/PHIF Output Data Strobe.
SIO2 Input Load/PHIF Input Data Strobe.
SIO2 Multiprocessor Synchronization/PHIF Byte Select.
SIO2 Data Output/PHIF Status Register Select.
SIO2 Output Clock/PHIF Chip Select Not.
SIO1 Data Output Enable.
SIO1 Multiprocessor Address.
SIO1 Multiprocessor Synchronization.
SIO1 Data Output.
SIO1 Output Load.
SIO1 Output Clock.
SIO1 Input Clock.
SIO1 Input Load.
SIO1 Data Input.
SIO1 Input Buffer Full.
SIO1 Output Buffer Empty.
Ground.
Power Supply.
Analog Power Supply.
Analog Ground.
* 3-states when RSTB = 0, or by JTAG control.
† 3-states when RSTB = 0 and INT0 = 1. Output = 1 when RSTB = 0 and INT0 = 0.
§ Pull-up devices on input.
‡ 3-states by JTAG control.
** See Section 7, Mask-Programmable Options.
†† For SIO multiprocessor applications, add 5 kΩ external pull-up resistors to SADD1 and/or SADD2 for proper initialization.
6
Lucent Technologies Inc.
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