EVAL-AD5755-1SDZ Просмотр технического описания (PDF) - Analog Devices

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EVAL-AD5755-1SDZ

Quad Channel, 16-Bit, Serial Input, 4 mA to 20 mA Output DAC, Dynamic Power Control, HART Connectivity

Analog Devices 

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

RSET_B 1

RSET_A 2

REFGND 3

REFGND 4

AD0 5

AD1 6

SYNC 7

SCLK 8

SDIN 9

SDO 10

DVDD 11

DGND 12

LDAC 13

CLEAR 14

ALERT 15

FAULT 16

AD5757

TOP VIEW

(Not to Scale)

48 COMPDCDC_C

47 IOUT_C

46 VBOOST_C

45 AVCC

44 SWC

43 GNDSWC

42

41

GSWNDDSWD

40 AGND

39 SWA

38 GNDSWA

37 GNDSWB

36 SWB

35 AGND

34 VBOOST_B

33 IOUT_B

AD5757

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED PAD SHOULD BE CONNECTED TO AGND, OR ALTERNATIVELY,

IT CAN BE LEFT ELECTRICALLY UNCONNECTED. IT IS RECOMMENDED THAT

THE PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED

THERMAL PERFORMANCE.

Figure 8. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1

RSET_B

An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_B

temperature drift performance. See the Device Features section.

2

RSET_A

An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_A

temperature drift performance. See the Device Features section.

3, 4

REFGND

Ground Reference Point for Internal Reference.

5

AD0

Address Decode for the Device Under Test (DUT) on the Board.

6

AD1

Address Decode for the DUT on the Board. It is not recommended to tie both AD1 and AD0 low when using PEC,

see the Packet Error Checking section.

7

SYNC

Active Low Input. This is the frame synchronization signalfor the serial interface. While SYNC is low, data is

transferred in on the falling edge of SCLK.

8

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This pin operates at

clock speeds of up to 30 MHz.

9

SDIN

Serial Data Input. Data must be valid on the falling edge of SCLK.

10

SDO

Serial Data Output. Used to clock data from the serial register in readback mode. See Figure 4 and Figure 6.

11

12, 17

DVDD

DGND

Digital Supply. The voltage range is from 2.7 V to 5.5 V.

Digital Ground.

13

LDAC

Load DAC, Active Low Input. This is used to update the DAC register and consequently the DAC outputs. When

tied permanently low, the addressed DAC data register is updated on the rising edge of SYNC. If LDAC is held

high during the write cycle, the DAC input register is updated, but the DAC output update only takes place at

the falling edge of LDAC (see Figure 3). Using this mode, all analog outputs can be updated simultaneously. The

LDAC pin must not be left unconnected.

14

CLEAR

Active High, Edge Sensitive Input. Asserting this pin sets the output current and voltage to the preprogrammed

clear code bit setting. Only channels enabled to be cleared are cleared. See the Device Features section for more

information. When CLEAR is active, the DAC output register cannot be written to.

Rev. G | Page 11 of 45

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