M25P16-VMN3 Просмотр технического описания (PDF) - Micron Technology

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M25P16-VMN3

Micron M25P16 Serial Flash Embedded Memory

Micron Technology 

Micron M25P16 Serial Flash Embedded Memory

Command Set Overview

Command Set Overview

All commands, addresses, and data are shifted in and out of the device, most significant

bit first.

Serial data inputs DQ0 and DQ1 are sampled on the first rising edge of serial clock (C)

after chip select (S#) is driven LOW. Then, the one-byte command code must be shifted

in to the device, most significant bit first, on DQ0 and DQ1, each bit being latched on

the rising edges of C.

Every command sequence starts with a one-byte command code. Depending on the

command, this command code might be followed by address or data bytes, by address

and data bytes, or by neither address or data bytes. For the following commands, the

shifted-in command sequence is followed by a data-out sequence. S# can be driven

HIGH after any bit of the data-out sequence is being shifted out.

• READ DATA BYTES (READ)

• READ DATA BYTES at HIGHER SPEED

• READ STATUS REGISTER

• READ IDENTIFICATION

• RELEASE from DEEP POWER-DOWN

For the following commands, S# must be driven HIGH exactly at a byte boundary. That

is, after an exact multiple of eight clock pulses following S# being driven LOW, S# must

be driven HIGH. Otherwise, the command is rejected and not executed.

• PAGE PROGRAM

• SECTOR ERASE

• BULK ERASE

• WRITE STATUS REGISTER

• WRITE ENABLE

• WRITE DISABLE

All attempts to access the memory array are ignored during a WRITE STATUS REGISTER

command cycle, a PROGRAM command cycle, or an ERASE command cycle. In addi-

tion, the internal cycle for each of these commands continues unaffected.

PDF: 09005aef8456656c

m25p16.pdf - Rev. J 1/18 EN

19

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2011 Micron Technology, Inc. All rights reserved.

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