M25P16-VMN3 Просмотр технического описания (PDF) - Micron Technology
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M25P16-VMN3 Datasheet PDF : 62 Pages
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Micron M25P16 Serial Flash Embedded Memory
Operating Features
Table 6: Protected Area Sizes (Continued)
Status Register Content
BP Bit 2
BP Bit 1
BP Bit 0
1
1
1
Protected Area
All sectors (sectors 0 to 31)
Memory Content
Unprotected Area
none
Note: 1. 0 0 0 = unprotected area (sectors): The device is ready to accept a BULK ERASE command
only if all block protect bits (BP2, BP1, BP0) are 0.
Table 7: Protected Area Sizes
Status Register Content
BP Bit 2
BP Bit 1
BP Bit 0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Memory Content
Protected Area
Unprotected Area
none
All sectors (sectors 0 to 63)
Upper 64th (sector 63)
Lower 63/64ths (sectors 0 to 62)
Upper 32nd (sectors 62 and 63)
Lower 31/32nds (sectors 0 to 61)
Upper 16th (sectors 60 and 63)
Lower 15/16ths (sectors 0 to 59)
Upper 8th (sectors 56 to 63)
Lower 7/8ths (sectors 0 to 55)
Upper 4th (sectors 48 to 63)
Lower 3/4ths (sectors 0 to 47)
Upper half (sectors 32 to 63)
Lower half (sectors 0 to 31)
All sectors (sectors 0 to 63)
none
Note: 1. 0 0 0 = unprotected area (sectors): The device is ready to accept a BULK ERASE command
only if all block protect bits (BP2, BP1, BP0) are 0.
Table 8: Protected Area Sizes
Status Register Content
BP Bit 2
BP Bit 1
BP Bit 0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Memory Content
Protected Area
Unprotected Area
none
All sectors (sectors 0 to 127)
Upper 64th (sectors 126 and 127)
Lower 63/64ths (sectors 0 to 125)
Upper 32nd (sectors 124 to 127)
Lower 31/32nds (sectors 0 to 123)
Upper 16th (sectors 120 to 127)
Lower 15/16ths (sectors 0 to 119)
Upper 8th (sectors 112 to 127)
Lower 7/8ths (sectors 0 to 111)
Upper 4th (sectors 96 to 127)
Lower 3/4ths (sectors 0 to 95)
Upper half (sectors 64 to 127)
Lower half (sectors 0 to 63)
All sectors (sectors 0 to 127)
none
Note: 1. The device is ready to accept a BULK ERASE command only if all block protect bits (BP2,
BP1, BP0) are 0.
Hold Condition
The HOLD# signal is used to pause any serial communications with the device without
resetting the clocking sequence. However, taking this signal LOW does not terminate
any WRITE STATUS REGISTER, PROGRAM, or ERASE cycle that is currently in progress.
PDF: 09005aef8456656c
m25p16.pdf - Rev. J 1/18 EN
15
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
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