74HC40105 Просмотр технического описания (PDF) - NXP Semiconductors.

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74HC40105

4-bit x 16-word FIFO register

NXP Semiconductors. 

NXP Semiconductors

74HC40105; 74HCT40105

4-bit x 16-word FIFO register

6.2 Data input

Following power-up, the master-reset (MR) input is pulsed HIGH to clear the FIFO

memory (see Figure 7). The data-in-ready flag (DIR = HIGH) indicates that the FIFO input

stage is empty and ready to receive data. When DIR is valid (HIGH), data present at D0 to

D3 can be shifted-in using the SI control input. With SI = HIGH, data is shifted into the

input stage. DIR going LOW provides a busy indication. The data remains at the first

location in the FIFO until DIR is set to HIGH and data moves through the FIFO to the

output stage, or to the last empty location. If the FIFO is not full after the SI pulse, DIR

again becomes valid (HIGH) to indicate that space is available in the FIFO. The DIR flag

remains LOW if the FIFO is full (see Figure 8). To complete the shift-in process, the SI use

must be made LOW. With the FIFO full, SI can be held HIGH until a shift-out (SO) pulse

occurs. Then, following a shift-out of data, an empty location appears at the FIFO input

and DIR goes HIGH to allow the next data to be shifted-in. This data remains at the first

FIFO location until SI goes LOW (see Figure 9).

6.3 Data transfer

After data has been transferred from the input stage of the FIFO following SI = LOW, data

moves through the FIFO asynchronously and is stacked at the output end of the register.

Empty locations appear at the input end of the FIFO as data moves through the device.

6.4 Data output

The data-out-ready flag (DOR = HIGH) indicates that there is valid data at the output (Q0

to Q3). The initial master-reset at power-on (MR = HIGH) sets DOR to LOW (see

Figure 7). After MR = LOW, data shifted into the FIFO moves through to the output stage

causing DOR to go HIGH. As the DOR flag goes HIGH, data can be shifted-out using the

SO = HIGH, data in the output stage is shifted out. DOR going LOW provides a busy

indication. When SO is made LOW, data moves through the FIFO to fill the output stage

and an empty location appears at the input stage. When the output stage is filled DOR

goes HIGH, but if the last of the valid data has been shifted-out leaving the FIFO empty

the DOR flag remains LOW (see Figure 11). With the FIFO empty, the last word that was

shifted-out is latched at the output Q0 to Q3.

With the FIFO empty, the SO input can be held HIGH until the SI control input is used.

Following an SI pulse, data moves through the FIFO to the output stage, resulting in the

DOR flag pulsing HIGH and a shift-out of data occurring. The SO control must be made

LOW before additional data can be shifted-out (see Figure 14).

6.5 High-speed burst mode

Assuming the shift-in/shift-out pulses are not applied until the respective status flags are

valid, it follows that the status flags determine the shift-in/shift-out rates. However, without

the status flags, a high-speed burst can be implemented. In this mode, pulse widths

determine the burst-in/ burst-out rates of the shift-in/shift-out inputs. Burst rates of 35 MHz

can be obtained. Shift pulses can be applied without regard to the status flags but shift-in

pulses that would overflow the storage capacity of the FIFO are not allowed (see

Figure 12 and Figure 13).

74HC_HCT40105

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 25 September 2013

© NXP B.V. 2013. All rights reserved.

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