74HC40105 Просмотр технического описания (PDF) - NXP Semiconductors.
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74HC40105 Datasheet PDF : 37 Pages
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NXP Semiconductors
74HC40105; 74HCT40105
4-bit x 16-word FIFO register
18. Contents
1
2
3
4
5
5.1
5.2
6
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.2
6.3
6.4
6.5
6.6
7
8
9
10
11
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11
11.12
12
12.1
12.1.1
12.1.2
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Inputs and outputs . . . . . . . . . . . . . . . . . . . . . . 5
Data inputs (D0 to D3) . . . . . . . . . . . . . . . . . . . 5
Data outputs (Q0 to Q3) . . . . . . . . . . . . . . . . . . 5
Master-reset (MR). . . . . . . . . . . . . . . . . . . . . . . 5
Status flag outputs (DIR, DOR). . . . . . . . . . . . . 5
Shift-in control (SI) . . . . . . . . . . . . . . . . . . . . . . 5
Shift-out control (SO) . . . . . . . . . . . . . . . . . . . . 5
Output enable (OE) . . . . . . . . . . . . . . . . . . . . . 5
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
High-speed burst mode . . . . . . . . . . . . . . . . . . 6
Expanded format . . . . . . . . . . . . . . . . . . . . . . . 7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions. . . . . . . . 8
Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Master reset applied with FIFO full . . . . . . . . . 15
Shifting in sequence FIFO empty to FIFO full. 16
With FIFO full; SI held HIGH in anticipation
of empty location . . . . . . . . . . . . . . . . . . . . . . 17
SO input to Qn outputs propagation delay . . . 17
Shifting out sequence; FIFO full to FIFO
empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Shift-in operation; high-speed burst mode . . . 18
Shift-out operation; high-speed burst mode . . 19
With FIFO empty; SO is held HIGH
in anticipation . . . . . . . . . . . . . . . . . . . . . . . . . 20
MR to SI recovery time . . . . . . . . . . . . . . . . . . 21
Enable and disable times . . . . . . . . . . . . . . . . 21
Set-up and hold times. . . . . . . . . . . . . . . . . . . 22
Test circuit for measuring switching times . . . 22
Application information. . . . . . . . . . . . . . . . . . 24
Expanded format . . . . . . . . . . . . . . . . . . . . . . 24
Sequence 1 (both FIFOs empty, starting
SHIFT-IN process) . . . . . . . . . . . . . . . . . . . . . 28
Sequence 2 (FIFOB runs full) . . . . . . . . . . . . . 28
12.1.3
12.1.4
12.1.5
12.1.6
13
14
15
16
16.1
16.2
16.3
16.4
17
18
Sequence 3 (FIFOA runs full) . . . . . . . . . . . . 29
Sequence 4 (both FIFOs full,
starting SHIFT-OUT) . . . . . . . . . . . . . . . . . . . 29
Sequence 5 (FIFOA runs empty) . . . . . . . . . . 29
Sequence 6 (FIFOB runs empty) . . . . . . . . . . 29
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 30
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 34
Revision history . . . . . . . . . . . . . . . . . . . . . . . 34
Legal information . . . . . . . . . . . . . . . . . . . . . . 35
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 35
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Contact information . . . . . . . . . . . . . . . . . . . . 36
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 September 2013
Document identifier: 74HC_HCT40105
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