74HC40105 Просмотр технического описания (PDF) - NXP Semiconductors.

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74HC40105

4-bit x 16-word FIFO register

NXP Semiconductors. 

NXP Semiconductors

74HC40105; 74HCT40105

4-bit x 16-word FIFO register

6. Functional description

6.1 Inputs and outputs

6.1.1 Data inputs (D0 to D3)

As there is no weighting of the inputs, any input can be assigned as the MSB. The size of

the FIFO memory can be reduced from the 4 x 16 configuration. For example, it can be

reduced to 3 x 16, down to 1 x 16, by tying unused data input pins to VCC or GND.

6.1.2 Data outputs (Q0 to Q3)

As there is no weighting of the outputs, any output can be assigned as the MSB. The size

of the FIFO memory can be reduced from the 4 x 16 configuration as described for data

inputs. In a reduced format, the unused data outputs pins must be left open circuit.

6.1.3 Master-reset (MR)

When MR is HIGH, the control functions within the FIFO are cleared, and date content is

declared invalid. The data-in ready (DIR) flag is set HIGH and the data-out-ready (DOR)

flag is set LOW. The output stage remains in the state of the last word that was shifted out,

or in the random state existing at power-up.

6.1.4 Status flag outputs (DIR, DOR)

Two status flags, data-in-ready (DIR) and data-out-ready (DOR), indicate the status of the

FIFO:

1. DIR = HIGH indicates that the input stage is empty and ready to accept valid data;

2. DIR = LOW indicates that the FIFO is full or that a previous shift-in operation is not

complete (busy);

3. DOR = HIGH assures valid data is present at the outputs Q0 to Q3 (does not indicate

that new data is awaiting transfer into the output stage);

4. DOR = LOW indicates that the output stage is busy or there is no valid data.

6.1.5 Shift-in control (SI)

Data is loaded into the input stage on a LOW-to-HIGH transition of SI. It also triggers an

automatic data transfer process (ripple through). If SI is held HIGH during reset, data is

loaded at the falling edge of the MR signal.

6.1.6 Shift-out control (SO)

A HIGH-to-LOW transition of SO causes the DOR flags to go LOW. A HIGH-to-LOW

transition of SO causes upstream data to move into the output stage, and empty locations

to move towards the input stage (bubble-up).

6.1.7 Output enable (OE)

The outputs Q0 to Q3 are enabled when OE = LOW. When OE = HIGH the outputs are in

the high impedance OFF-state.

74HC_HCT40105

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 25 September 2013

© NXP B.V. 2013. All rights reserved.

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