SM8578BV Просмотр технического описания (PDF) - Nippon Precision Circuits

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SM8578BV

Real-time Clock IC

Nippon Precision Circuits  

SM8578BV

Control Register 2 (Register F)

This register controls the clock timing frequency divider.

Address Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

F

*

TEST

*

RESET HOLD

*

*

*

I TEST bit: NPC Test Bit

This bit should be set to “0” when power is applied and when writing to register F.

I RESET bit

When this bit is set to “1”, the 2kHz to 1Hz frequency divider counters are reset and clock timing stops.

After “1” data is written, test mode is cancelled by writing “0” data or by setting the CE input LOW.

It is not affected by the state of any other bits.

I HOLD bit

When this bit is set to “1”, the seconds digit increment operation is disabled.

However, if an increment operation occurs when this bit is “1” and the bit is subsequently set to “0” within 1

second, the automatic correction function forces a 1-second correction.

Therefore, it is recommended that the HOLD bit should be used for less than 1 second.

I Functional operation table

The function of the RESET and HOLD bits is shown in the following table.

Bit

Function

RESET HOLD

Clock timing

Timer interrupt output Alarm interrupt output

0

0

0

1

1

0

1

1

Operating

*1

Stopped

Stopped

Operating

*2

*3

*3

Operating

Stopped

Stopped

Stopped

*1. The automatic correction function operates if the HOLD bit is set for less than 1 second.

*2. Normal operation for source clocks other than 1/60Hz (1 minute).

*3. Normal operation for 4096Hz source clock only.

*4. Normal operation for 32768Hz source clock only.

Arbitrary frequency

output

Operating

Operating

*4

*4

NIPPON PRECISION CIRCUITS INC.—10

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