SM8578BV Просмотр технического описания (PDF) - Nippon Precision Circuits

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SM8578BV

Real-time Clock IC

Nippon Precision Circuits  

SM8578BV

Alarm Registers (Registers 7 to A)

I These registers contain the alarm interrupt time setting. When the alarm matches the clock registers, the

INTN output goes LOW (if the alarm interrupt enable AIE bit is set to 1).

I The alarm can be set for day-of-week, day, hour and minute.

Bit 7 of each of the alarm registers is an enable alarm AE bit. These bits can be used to implement repetitive

alarms, such as for every hour or every day.

I The day-of-week alarm can optionally be set for multiple alarms.

Correct alarm output may not occur if the only alarm setting is a day-of-week alarm.

I When the AE bit is set to 0, the alarm registers are compared with the corresponding clock registers. When

set to “1”, the data is ignored as don’t care bits and is always deemed to match.

I When the AIE bit in register E is set to “0”, output on pin INTN is disabled. The TIE and FE bits must be set

to “1” and the AIE bit must be set to “0” to enable alarm interrupts.

I Day-of-week alarm bit relationship.

Bit

Day-of-week

Bit6

Saturday

Bit5

Friday

Bit4

Thursday

Bit3

Wednesday

Bit2

Tuesday

Bit1

Monday

Bit0

Sunday

Timer Registers (Registers C to E)

I These registers control the 8-bit presettable down-counters used for timer interrupts. The counter source

clock is assigned by register C, and the counter frequency divider is assigned by register D.

I When the timer count register counts down to zero, with source clock cycle timing, the INTN output goes

LOW (if the timer interrupt enable TIE bit is set to “1”).

When the TI/TP bit is set to “1”, the fixed-cycle counter register data is reloaded and the count down starts

again. Accordingly, this bit can be used to implement an interval timer (periodic mode).

I When the TIE bit in register E is set to “0”, output on INTN is disabled.

The TI/TP, FE, AIE, and TIE bits must be set for normal timer operation (with the FE and AIE bits set to

“0”).

I When data is written to register D, the presettable down counters are updated. The data written to register D

is maintained until a subsequent data write is performed, hence this register can be used as RAM, similar to

the “*”- entries in the register table, when timer interrupt mode is not used (when TIE is “0”).

I When the TE bit is set to “0”, the counter loads the fixed-cycle counter contents and the count stops. When

the TE bit is set to “1”, the count starts.

I Note that when the TE bit is set to “0”, fixed-cycle interrupts from output INTN are not generated even when

the fixed-cycle counter (register D) is loaded with zero data.

TD1

TD0

Source clock

0

0

4096Hz

0

1

64Hz

1

0

1Hz

1

1

1/60Hz

NIPPON PRECISION CIRCUITS INC.—8

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