A54SX08A Просмотр технического описания (PDF) - Actel Corporation
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A54SX08A Datasheet PDF : 108 Pages
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SX-A Family FPGAs
Input Buffer Delays
PAD
Y
INBUF
In
Out
GND
3V
1.5 V 1.5 V
VCC
50%
0V
50%
tINY
tINY
Figure 2-6 • Input Buffer Delays
Cell Timing Characteristics
C-Cell Delays
S
AY
B
S, A, or B
Out
GND
Out
VCC
50% 50%
VCC
50%
GND
50%
tPD
50%
tPD
tPD
GND
tPD
VCC
50%
Figure 2-7 • C-Cell Delays
D
CLK
tSUD
Q
CLR
PRESET
D PRESET Q
CLK
CLR
(Positive Edge Triggered)
t HD
ttHRPPWWHH
tRCO
ttHRPPWWLL
tHP
tCLR
tWASYN
tPRESET
Figure 2-8 • Flip-Flops
2-16
v5.3
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