A54SX08A Просмотр технического описания (PDF) - Actel Corporation
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A54SX08A Datasheet PDF : 108 Pages
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SX-A Family FPGAs
Table 2-16 • A54SX08A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70°C)
–2 Speed
–1 Speed Std. Speed
–F Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hardwired) Array Clock Networks
tHCKH
Input Low to High
(Pad to R-cell Input)
1.3
1.5
1.7
2.6
ns
tHCKL
Input High to Low
(Pad to R-cell Input)
1.1
1.3
1.5
2.2
ns
tHPWH
Minimum Pulse Width High
tHPWL
Minimum Pulse Width Low
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
Routed Array Clock Networks
1.6
1.8
2.1
2.9
ns
1.6
1.8
2.1
2.9
ns
0.4
0.5
0.5
0.8
ns
3.2
3.6
4.2
5.8
ns
313
278
238
172 MHz
tRCKH
Input Low to High (Light Load)
(Pad to R-cell Input)
0.8
0.9
1.1
1.5
ns
tRCKL
Input High to Low (Light Load)
(Pad to R-cell Input)
1.1
1.2
1.4
2
ns
tRCKH
Input Low to High (50% Load)
(Pad to R-cell Input)
0.8
0.9
1.1
1.5
ns
tRCKL
Input High to Low (50% Load)
(Pad to R-cell Input)
1.1
1.2
1.4
2
ns
tRCKH
Input Low to High (100% Load)
(Pad to R-cell Input)
1.1
1.2
1.4
1.9
ns
tRCKL
Input High to Low (100% Load)
(Pad to R-cell Input)
1.2
1.3
1.6
2.2
ns
tRPWH
tRPWL
tRCKSW
tRCKSW
tRCKSW
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
1.6
1.8
2.1
2.9
ns
1.6
1.8
2.1
2.9
ns
0.7
0.8
0.9
1.3
ns
0.7
0.8
0.9
1.3
ns
0.8
0.9
1.1
1.5
ns
v5.3
2-21
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