A54SX08A Просмотр технического описания (PDF) - Actel Corporation
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A54SX08A Datasheet PDF : 108 Pages
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SX-A Family FPGAs
SX-A Timing Model
Input Delays
I/O Module
tINYH= 0.6 ns
tRD1 = 0.3 ns
tRD2 = 0.5 ns
Internal Delays
Combinatorial
Cell
Predicted
Routing
Delays
Output Delays
I/O Module
tPD = 1.1 ns
Register
Cell
tttRRRDDD841
=
=
=
0.3
0.9
1.5
ns
ns
ns
tDHL = 3.9 ns
I/O Module
tDHL = 3.9 ns
D
t
t
SUD = 0.8 ns
HD = 0.0 ns
Q
tRD1 = 0.3 ns
Routed
Clock
tRCKH = 3.0 ns
(100% Load)
tRCO= 0.8 ns
I/O Module
tINYH= 0.6 ns
Register
Cell
DQ
tSUD = 0.8 ns
tRD1 = 0.3 ns
tHD = 0.0 ns
Hardwired
Clock
tHCKH= 1.8 ns
tRCO= 0.8 ns
tENZL= 1.5 ns
I/O Module
tDHL = 3.9 ns
tENZL= 1.5 ns
Note: *Values shown for A54SX72A, –2, worst-case commercial conditions at 5 V PCI with standard place-and-route.
Figure 2-3 • SX-A Timing Model
Sample Path Calculations
Hardwired Clock
External Setup
= (tINYH + tRD1 + tSUD) – tHCKH
= 0.6 + 0.3 + 0.8 - 1.8 = – 0.1 ns
Clock-to-Out (Pad-to-Pad) = tHCKH + tRCO + tRD1 + tDHL
= 1.8 + 0.8 + 0.3 + 3.9 = 6.8 ns
Routed Clock
External Setup
= (tINYH + tRD1 + tSUD) – tRCKH
= 0.6 + 0.3 + 0.8 - 3.0 = –1.3 ns
Clock-to-Out (Pad-to-Pad) = tRCKH + tRCO + tRD1 + tDHL
= 3.0 + 0.8 + 0.3 + 3.9 = 8.0 ns
2-14
v5.3
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