A54SX08A Просмотр технического описания (PDF) - Actel Corporation

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A54SX08A

SX-A Family FPGAs

Actel Corporation 

SX-A Family FPGAs

Table 2-10 • AC Specifications (3.3 V PCI Operation)

Symbol Parameter

Condition

Min.

Max.

Units

IOH(AC)

Switching Current High

0 < VOUT ≤ 0.3VCCI 1

0.3VCCI ≤ VOUT < 0.9VCCI 1

0.7VCCI < VOUT < VCCI 1, 2

–12VCCI

(–17.1(VCCI – VOUT))

–

–

mA

–

mA

EQ 2-3 on

–

page 2-7

IOL(AC)

(Test Point)

Switching Current Low

VOUT = 0.7VCC 2

VCCI > VOUT ≥ 0.6VCCI 1

0.6VCCI > VOUT > 0.1VCCI 1

0.18VCCI > VOUT > 0 1, 2

–

16VCCI

(26.7VOUT)

–

–32VCCI

mA

–

mA

–

mA

EQ 2-4 on

–

page 2-7

(Test Point)

VOUT = 0.18VCC 2

–

38VCCI

mA

ICL

Low Clamp Current

–3 < VIN ≤ –1

–25 + (VIN + 1)/0.015

–

mA

ICH

High Clamp Current

VCCI + 4 > VIN ≥ VCCI + 1

25 + (VIN – VCCI – 1)/0.015

–

mA

slewR

Output Rise Slew Rate

0.2VCCI - 0.6VCCI load 3

1

4

V/ns

slewF

Output Fall Slew Rate

0.6VCCI - 0.2VCCI load 3

1

4

V/ns

Notes:

1. Refer to the V/I curves in Figure 2-2 on page 2-7. Switching current characteristics for REQ# and GNT# are permitted to be one half

of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#,

which are system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#,

which are open drain outputs.

2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C

and D) are provided with the respective diagrams in Figure 2-2 on page 2-7. The equation defined maximum should be met by

design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.

3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any

point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter

with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and

minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain

outputs.

Pin

Output

Buffer

1 k/25 Ω

1/2 in. max.

10 pF

Pin

Output

Buffer

1 k/25 Ω

10 pF

2-6

v5.3

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