ST72C314N4 Просмотр технического описания (PDF) - STMicroelectronics

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ST72C314N4

8-bit MCU for automotive with single voltage Flash/ROM memory, ADC, 16-bit timers, SPI, SCI interfaces

STMicroelectronics 

ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto

DATA EEPROM (Cont’d)

6.3 MEMORY ACCESS

The Data EEPROM memory read/write access

modes are controlled by the LAT bit of the EEP-

ROM Control/Status register (EECSR). The flow-

chart in Figure 7 describes these different memory

access modes.

Read Operation (LAT=0)

The EEPROM can be read as a normal ROM loca-

tion when the LAT bit of the EECSR register is

cleared. In a read cycle, the byte to be accessed is

put on the data bus in less than 1 CPU clock cycle.

This means that reading data from EEPROM

takes the same time as reading data from

EPROM, but this memory cannot be used to exe-

cute machine code.

Write Operation (LAT=1)

To access the write mode, the LAT bit has to be

set by software (the PGM bit remains cleared).

When a write access to the EEPROM area occurs,

the value is latched inside the 16 data latches ac-

cording to its address.

When PGM bit is set by the software, all the previ-

ous bytes written in the data latches (up to 16) are

programmed in the EEPROM cells. The effective

high address (row) is determined by the last EEP-

ROM write sequence. To avoid wrong program-

ming, the user must take care that all the bytes

written between two programming sequences

have the same high address: only the four Least

Significant Bits of the address can change.

At the end of the programming cycle, the PGM and

LAT bits are cleared simultaneously, and an inter-

rupt is generated if the IE bit is set. The Data EEP-

ROM interrupt request is cleared by hardware

when the Data EEPROM interrupt vector is

fetched.

Note: Care should be taken during the program-

ming cycle. Writing to the same memory location

will over-program the memory (logical AND be-

tween the two write access data result) because

the data latches are only cleared at the end of the

programming cycle and by the falling edge of LAT

bit.

It is not possible to read the latched data.

This note is illustrated by the Figure 8.

Figure 7. Data EEPROM Programming Flowchart

READ MODE

LAT=0

PGM=0

WRITE MODE

LAT=1

PGM=0

READ BYTES

IN EEPROM AREA

WRITE UP TO 16 BYTES

IN EEPROM AREA

(with the same 11 MSB of the address)

START PROGRAMMING CYCLE

LAT=1

PGM=1 (set by software)

INTERRUPT GENERATION

IF IE=1

CLEARED BY HARDWARE

0

1

LAT

20/150

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