ALC202 Просмотр технического описания (PDF) - Realtek Semiconductor

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ALC202

TWO CHANNEL AC97 AUDIO CODEC

Realtek Semiconductor 

ALC202/ALC202A

6.3.3 MX7A Various Controls

Default: 57C0h

This register is used for several types of information.

Bit Type

Function

15

R Clock Source Selection: (XTLSEL)

1: 14.318MHz crystal is used. 14.318M 24.576M digital PLL is enabled. (XTLSEL is pulled low)

0: 24.576MHz crystal is used. DPLL is bypassed. (XTLSEL is floating or open)

14

R/W Buffer Under-run Policy: (BUP)

1: Hold a zero PCM sample when FIFO is under-run

0: Hold the last PCM sample when FIFO is under-run

13

R/W Digital High-pass Filter to Eliminate Variation in DC Offset: (ENHPF)

1: Enabled (default) 0: Disabled

12

R/W Enable DC Voltage Volume Control:

1: Enable. Master volume and headphone volume are determined by the sum of the 5-bit volume code and

MX02/MX04/MX06.

0: Disable. Reset 5-bit volume code to 0.

11:8

NA Reserved

7

R/W Pin-48 Function Selection:

1: TEST 0: S/PDIF output (default)

6

R/W Output value of TEST: (when bit-7 is set)

1: DAC CLK 0: ADC CLK

5

R/W Pin-47 Function Selection:

1: Jack-Detect input 0: EAPD output (default)

4

R/W HP-OUT Control:

1: HP-OUT is auto muted by H/W when JDS=1

0: Normal

3

R/W MONO-OUT Control:

1: MONO-OUT is auto muted by H/W when JDS=1

0: Normal

2

R/W SPDIF Output Gating:

1: SPDIF output is gated with JDS

0: SPDIF output is not gated with JDS

1

R Jack-Detect Status: (JDS)

1: JD is floating or pulled high

0: JD is pulled low

This bit always indicates the JD pin status after power on.

0

R/W LINE-OUT Control:

1: LINE-OUT is auto muted by H/W when JDS=1

0: Normal

2002/07/30

23

Rev.1.28

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