SAA7127 Просмотр технического описания (PDF) - Philips Electronics

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производитель

SAA7127

Digital video encoder

Philips Electronics 

Philips Semiconductors

Digital video encoder

Product specification

SAA7126H; SAA7127H

7.10 I2C-bus format

Table 4 I2C-bus address; see Table 5

S

SLAVE ADDRESS ACK SUBADDRESS ACK DATA 0

ACK --------

DATA n ACK P

Table 5 Explanation of Table 4

PART

S

SLAVE ADDRESS

ACK

SUBADDRESS; note 2

DATA

--------

P

DESCRIPTION

START condition

1000 100X or 1000 110X; note 1

acknowledge, generated by the slave

subaddress byte

data byte

continued data bytes and ACKs

STOP condition

Notes

1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read.

2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed.

7.11 Slave receiver

Table 6 Subaddresses 26H and 27H

DATA BYTE

WSS

WSSON

LOGIC

LEVEL

−

0

1

DESCRIPTION

wide screen signalling bits

3 to 0 = aspect ratio

7 to 4 = enhanced services

10 to 8 = subtitles

13 to 11 = reserved

wide screen signalling output is disabled; default after reset

wide screen signalling output is enabled

Table 7 Subaddress 28H

DATA BYTE

BS

DECCOL

DECFIS

LOGIC

LEVEL

−

0

1

0

1

DESCRIPTION

REMARKS

starting point of burst in clock cycles

PAL: BS = 33 (21H); default after reset

NTSC: BS = 25 (19H)

disable colour detection bit of RTCI input

enable colour detection bit of RTCI input bit RTCE must be set to logic 1 (see Fig.13)

field sequence as FISE in subaddress 61

field sequence as FISE bit in RTCI input bit RTCE must be set to logic 1 (see Fig.13)

2002 Oct 15

13

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