SAA7127 Просмотр технического описания (PDF) - Philips Electronics

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производитель

SAA7127

Digital video encoder

Philips Electronics 

Philips Semiconductors

Digital video encoder

Product specification

SAA7126H; SAA7127H

Table 30 Subaddress 6DH

DATA BYTE

DESCRIPTION

VTRIG

sets the vertical trigger phase related to signal on RCV1 input

increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;

variation range of VTRIG = 0 to 31 (1FH)

Table 31 Subaddress 6EH

DATA BYTE

SBLBN

BLCKON

PHRES

LDEL

FLC

LOGIC

LEVEL

DESCRIPTION

0 vertical blanking is defined by programming of FAL and LAL; default after reset

1 vertical blanking is forced in accordance with “CCIR 624” (50 Hz) or RS170A (60 Hz)

0 encoder in normal operation mode

1 output signal is forced to blanking level; default after reset

− selects the phase reset mode of the colour subcarrier generator; see Table 32

− selects the delay on luminance path with reference to chrominance path; see Table 33

− field length control; see Table 34

Table 32 Logic levels and function of PHRES

DATA BYTE

PHRES1

0

0

1

1

PHRES0

0

1

0

1

DESCRIPTION

no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset

reset every two lines

reset every eight fields

reset every four fields

Table 33 Logic levels and function of LDEL

DATA BYTE

LDEL1

0

0

1

1

LDEL0

0

1

0

1

DESCRIPTION

no luminance delay; default after reset

1 LLC luminance delay

2 LLC luminance delay

3 LLC luminance delay

Table 34 Logic levels and function of FLC

DATA BYTE

FLC1

0

0

1

1

FLC0

0

1

0

1

DESCRIPTION

interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset

non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz

non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz

non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz

2002 Oct 15

21

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