BD82HM55-SLGZS Просмотр технического описания (PDF) - Intel

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Компоненты Описание

производитель

BD82HM55-SLGZS

Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Intel 

5.22

5.23

5.24

5.25

5.26

5.27

5.28

Intel®

5.22.1

5.21.2.9 Case for Considerations ........................................................

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Audio Overview

Definition Audio

(D27:F0)...................................................

Docking (Mobile Only) ................................

250

252

252

5.22.1.1 Dock Sequence ................................................................... 252

5.22.1.2 Exiting D3/CRST# when Docked ............................................ 253

5.22.1.3 Cold Boot/Resume from S3 When Docked ............................... 254

5.22.1.4 Undock Sequence ................................................................ 254

5.22.1.5 Normal Undock.................................................................... 254

5.22.1.6 Surprise Undock .................................................................. 255

5.22.1.7 Interaction Between Dock/Undock and Power Management

States ................................................................................ 255

Intel®

5.23.1

5.23.2

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255

256

257

257

Serial Peripheral Interface (SPI) ........................................................................ 258

5.24.1 SPI Supported Feature Overview ......................................................... 258

5.24.1.1 Non-Descriptor Mode ........................................................... 258

5.24.1.2 Descriptor Mode .................................................................. 258

5.24.1.3 Device Partitioning............................................................... 260

5.24.2 Flash Descriptor ................................................................................ 260

5.24.2.1 Descriptor Master Region ...................................................... 262

5.24.3 Flash Access ..................................................................................... 263

5.24.3.1 Direct Access Security .......................................................... 263

5.24.3.2 Register Access Security ....................................................... 263

5.24.4 Serial Flash Device Compatibility Requirements ..................................... 264

5.24.4.1 PCH SPI Based BIOS Requirements ........................................ 264

5.24.4.2

5.24.4.3

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264

265

5.24.4.4 Hardware Sequencing Requirements ...................................... 265

5.24.5 Multiple Page Write Usage Model.......................................................... 266

5.24.5.1 Soft Flash Protection ............................................................ 266

5.24.5.2 BIOS Range Write Protection................................................. 267

5.24.5.3 SMI# Based Global Write Protection ....................................... 267

5.24.6 Flash Device Configurations ................................................................ 267

5.24.7 SPI Flash Device Recommended Pinout................................................. 267

5.24.8 Serial Flash Device Package ................................................................ 268

5.24.8.1 Common Footprint Usage Model ............................................ 268

Intel®

5.24.8.2 Serial Flash

Quiet System Technology

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268

269

5.25.1 PWM Outputs .................................................................................... 269

5.25.2 TACH Inputs ..................................................................................... 269

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269

270

5.27.1 Analog Display Interface Characteristics................................................ 270

5.27.1.1 Integrated RAMDAC ............................................................. 271

5.27.1.2 DDC (Display Data Channel) ................................................. 271

5.27.2 Digital Display Interfaces .................................................................... 271

5.27.2.1 LVDS (Mobile only) .............................................................. 271

5.27.2.2 LVDS Pair States ................................................................. 272

5.27.2.3 Single Channel versus Dual Channel Mode .............................. 273

5.27.2.4 Panel Power Sequencing ....................................................... 273

5.27.2.5 LVDS DDC .......................................................................... 274

5.27.2.6 High Definition Multimedia Interface....................................... 274

5.27.2.7 Digital Video Interface (DVI) ................................................. 275

5.27.2.8 Display Port* ...................................................................... 275

5.27.2.9 Embedded DisplayPort.......................................................... 275

5.27.2.10 DisplayPort Aux Channel....................................................... 276

5.27.2.11 DisplayPort Hot-Plug Detect (HPD) ......................................... 276

5.27.2.12 Integrated Audio over HDMI and DisplayPort ........................... 276

5.27.2.13 Serial Digital Video Out (SDVO) ............................................. 276

5.27.2.14 Control Bus......................................................................... 277

5.27.3 Mapping of Digital Display Interface Signals .......................................... 278

5.27.4 Multiple Display Configurations ............................................................ 279

5.27.5

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Content Protection (HDCP) .................................

Interconnect .....................................................

Virtualization Technology ........................................................................

279

280

280

8

Datasheet

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