BD82HM55-SLGZS Просмотр технического описания (PDF) - Intel

Номер в каталоге

Компоненты Описание

производитель

BD82HM55-SLGZS

Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Intel 

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)

23.10.11 KTMSR—KT Modem Status Register (KT—D23:F3)

Address Offset: 06h

Default Value: 00h

Attribute:

Size:

RO

8 bits

The functionality of the Modem is emulated by the FW. This register provides the status

of the current state of the control lines from the modem.

Bit

Description

7

Data Carrier Detect (DCD)—RO. In Loop Back mode this bit is connected by

hardware to the value of MCR bit 3.

6

Ring Indicator (RI)—RO. In Loop Back mode this bit is connected by hardware to

the value of MCR bit 2.

5

Data Set Ready (DSR)—RO. In Loop Back mode this bit is connected by hardware

to the value of MCR bit 0.

4

Clear To Send (CTS)—RO. In Loop Back mode this bit is connected by hardware to

the value of MCR bit 1.

3

Delta Data Carrier Detect (DDCD)—RO. This bit is set when bit 7 is changed. This

bit is cleared by hardware when the MSR register is being read by the HOST driver.

Trailing Edge of Read Detector (TERI)—RO. This bit is set when bit 6 is changed

2

from 1 to 0. This bit is cleared by hardware when the MSR register is being read by

the Host driver.

1

Delta Data Set Ready (DDSR)—RO. This bit is set when bit 5 is changed. This bit is

cleared by hardware when the MSR register is being read by the Host driver.

0

Delta Clear To Send (DCTS)—RO. This bit is set when bit 4 is changed. This bit is

cleared by hardware when the MSR register is being read by the Host driver.

§§

956

Datasheet

Share Link: