BD82HM55-SLGZS Просмотр технического описания (PDF) - Intel

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Компоненты Описание

производитель

BD82HM55-SLGZS

Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Intel 

5.17

5.18

5.19

5.20

5.21

5.16.11.1 Mechanism ......................................................................... 207

5.16.11.2 Message Format.................................................................. 208

5.16.11.3 LED Message Type .............................................................. 209

5.16.11.4 SGPIO Waveform ................................................................ 210

5.16.12 External SATA................................................................................... 211

High Precision Event Timers.............................................................................. 211

5.17.1 Timer Accuracy ................................................................................. 211

5.17.2 Interrupt Mapping ............................................................................. 212

5.17.3 Periodic vs. Non-Periodic Modes .......................................................... 212

5.17.4 Enabling the Timers........................................................................... 213

5.17.5 Interrupt Levels ................................................................................ 213

5.17.6 Handling Interrupts ........................................................................... 214

5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors........................... 214

USB EHCI Host Controllers (D29:F0 and D26:F0)................................................. 215

5.18.1 EHC Initialization............................................................................... 215

5.18.1.1 BIOS Initialization ............................................................... 215

5.18.1.2 Driver Initialization .............................................................. 215

5.18.1.3 EHC Resets ........................................................................ 215

5.18.2 Data Structures in Main Memory ......................................................... 215

5.18.3 USB 2.0 Enhanced Host Controller DMA................................................ 216

5.18.4 Data Encoding and Bit Stuffing............................................................ 216

5.18.5 Packet Formats ................................................................................. 216

5.18.6 USB 2.0 Interrupts and Error Conditions............................................... 216

5.18.6.1 Aborts on USB 2.0-Initiated Memory Reads ............................ 217

5.18.7 USB 2.0 Power Management ............................................................... 217

5.18.7.1 Pause Feature..................................................................... 217

5.18.7.2 Suspend Feature ................................................................. 217

5.18.7.3 ACPI Device States.............................................................. 218

5.18.7.4 ACPI System States............................................................. 218

5.18.8 USB 2.0 Legacy Keyboard Operation .................................................... 218

5.18.9 USB 2.0 Based Debug Port ................................................................. 219

5.18.9.1 Theory of Operation............................................................ 219

5.18.10 EHCI Caching ................................................................................... 224

5.18.11 USB Pre-Fetch Based Pause ................................................................ 224

5.18.12 Function Level Reset Support (FLR) ..................................................... 224

5.18.12.1 FLR Steps .......................................................................... 224

5.18.13 USB Overcurrent Protection ................................................................ 225

Integrated USB 2.0 Rate Matching Hub .............................................................. 226

5.19.1 Overview ......................................................................................... 226

5.19.2 Architecture ..................................................................................... 226

SMBus Controller (D31:F3) ............................................................................... 227

5.20.1 Host Controller ................................................................................. 227

5.20.1.1 Command Protocols............................................................. 228

5.20.2 Bus Arbitration.................................................................................. 231

5.20.3 Bus Timing ....................................................................................... 232

5.20.3.1 Clock Stretching.................................................................. 232

5.20.3.2 Bus Time Out (The PCH as SMBus Master) .............................. 232

5.20.4 Interrupts / SMI#.............................................................................. 232

5.20.5 SMBALERT# ..................................................................................... 233

5.20.6 SMBus CRC Generation and Checking................................................... 233

5.20.7 SMBus Slave Interface ....................................................................... 234

5.20.7.1 Format of Slave Write Cycle.................................................. 234

5.20.7.2 Format of Read Command .................................................... 236

5.20.7.3 Slave Read of RTC Time Bytes .............................................. 238

5.20.7.4 Format of Host Notify Command ........................................... 238

Thermal Management ...................................................................................... 240

5.21.1 Thermal Sensor ................................................................................ 240

5.21.1.1 Internal Thermal Sensor Operation ........................................ 240

5.21.2 Thermal Reporting Over System Management Link 1 Interface (SMLink1) . 241

5.21.2.1

5.21.2.2

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242

243

5.21.2.3 Block Read Command .......................................................... 243

5.21.2.4 Read Data Format ............................................................... 245

5.21.2.5 Thermal Data Update Rate ................................................... 246

5.21.2.6 Temperature Comparator and Alert ....................................... 247

5.21.2.7 BIOS Set Up ....................................................................... 248

5.21.2.8 SMBus Rules....................................................................... 249

Datasheet

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