BD82HM55-SLGZS Просмотр технического описания (PDF) - Intel
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BD82HM55-SLGZS Datasheet PDF : 956 Pages
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5.14
5.15
5.16
5.13.6.5 LPC Devices and CLKRUN# ................................................... 178
5.13.7 Sleep States ..................................................................................... 178
5.13.7.1 Sleep State Overview ........................................................... 178
5.13.7.2 Initiating Sleep State ........................................................... 178
5.13.7.3 Exiting Sleep States ............................................................. 179
5.13.7.4 PCI Express* WAKE# Signal and PME Event Message ............... 181
5.13.7.5 Sx-G3-Sx, Handling Power Failures ........................................ 181
5.13.8 Event Input Signals and Their Usage .................................................... 181
5.13.8.1 PWRBTN# (Power Button) .................................................... 182
5.13.8.2 RI# (Ring Indicator) ............................................................ 183
5.13.8.3 PME# (PCI Power Management Event).................................... 183
5.13.8.4 SYS_RESET# Signal ............................................................. 183
5.13.8.5 THRMTRIP# Signal............................................................... 183
5.13.9 ALT Access Mode ............................................................................... 184
5.13.9.1 Write Only Registers with Read Paths in ALT Access Mode ......... 185
5.13.9.2 PIC Reserved Bits ................................................................ 187
5.13.9.3 Read Only Registers with Write Paths in ALT Access Mode ......... 187
5.13.10 System Power Supplies, Planes, and Signals.......................................... 187
5.13.10.1 Power Plane Control with SLP_S3#,
SLP_S4#, SLP_S5#, SLP_M# and SLP_LAN# .......................... 187
5.13.10.2 SLP_S4# and Suspend-To-RAM Sequencing ............................ 188
5.13.10.3 PWROK Signal ..................................................................... 188
5.13.10.4 BATLOW# (Battery Low) (Mobile Only) ................................... 188
5.13.10.5 SLP_LAN# Pin Behavior ........................................................ 189
5.13.10.6 RTCRST# and SRTCRST# ..................................................... 189
5.13.11 Clock Generators ............................................................................... 189
5.13.12 Legacy Power Management Theory of Operation .................................... 190
5.13.12.1 APM Power Management (Desktop Only)................................. 190
5.13.12.2 Mobile APM Power Management (Mobile Only) ......................... 190
5.13.13 Reset Behavior .................................................................................. 190
System Management (D31:F0) .......................................................................... 192
5.14.1 Theory of Operation ........................................................................... 193
5.14.1.1 Detecting a System Lockup ................................................... 193
5.14.1.2 Handling an Intruder ............................................................ 193
5.14.1.3 Detecting Improper Flash Programming .................................. 193
5.14.1.4 Heartbeat and Event Reporting using SMLink/SMBus ................ 193
5.14.2 TCO Modes ....................................................................................... 194
5.14.2.1 TCO Legacy/Compatible Mode ............................................... 194
5.14.2.2 Advanced TCO Mode ............................................................ 195
General Purpose I/O (D31:F0) ........................................................................... 197
5.15.1 Power Wells ...................................................................................... 197
5.15.2 SMI# SCI and NMI Routing ................................................................. 197
5.15.3 Triggering......................................................................................... 197
5.15.4 GPIO Registers Lockdown ................................................................... 197
5.15.5 Serial POST Codes Over GPIO.............................................................. 198
5.15.5.1 Theory of operation ............................................................. 198
5.15.5.2 Serial Message Format ......................................................... 199
SATA Host Controller (D31:F2, F5)..................................................................... 200
5.16.1 SATA Feature Support ........................................................................ 201
5.16.2 Theory of Operation ........................................................................... 202
5.16.2.1 Standard ATA Emulation ....................................................... 202
5.16.2.2 48-Bit LBA Operation ........................................................... 202
5.16.3 SATA Swap Bay Support ..................................................................... 202
5.16.4 Hot Plug Operation............................................................................. 202
5.16.4.1 Low Power Device Presence Detection .................................... 202
5.16.5 Function Level Reset Support (FLR)...................................................... 203
5.16.6
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5.16.6.1
FLR Steps ........................................................................... 203
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203
204
5.16.7 Power Management Operation ............................................................. 204
5.16.7.1 Power State Mappings .......................................................... 204
5.16.7.2 Power State Transitions ........................................................ 205
5.16.7.3 SMI Trapping (APM) ............................................................. 206
5.16.8 SATA Device Presence ........................................................................ 206
5.16.9 SATA LED ......................................................................................... 207
5.16.10 AHCI Operation ................................................................................. 207
5.16.11 SGPIO Signals ................................................................................... 207
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